Graphene-on-semiconductor substrates for analog electronics
US-9324804-B2 · Apr 26, 2016 · US
US9761669B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9761669-B1 |
| Application number | US-201615212413-A |
| Country | US |
| Kind code | B1 |
| Filing date | Jul 18, 2016 |
| Priority date | Jul 18, 2016 |
| Publication date | Sep 12, 2017 |
| Grant date | Sep 12, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Graphene nanoribbon arrays, methods of growing graphene nanoribbon arrays, and electronic and photonic devices incorporating the graphene nanoribbon arrays are provided. The graphene nanoribbons in the arrays are formed using a seed-mediated, bottom-up, chemical vapor deposition (CVD) technique in which the (001) facet of a semiconductor substrate and the orientation of the seed particles on the substrate are used to orient the graphene nanoribbon crystals preferentially along a single [110] direction of the substrate.
Opening claim text (preview).
What is claimed is: 1. A graphene nanoribbon array comprising: a semiconductor substrate having a (001) facet; and a plurality of graphene nanoribbons on the (001) facet of the semiconductor substrate; wherein the graphene nanoribbons have aspect ratios of at least 4; and further wherein the graphene nanoribbons have an armchair crystallographic direction of graphene running all the way along their long axes and an armchair configuration along their edges, and further wherein at least 60 percent of the graphene nanoribbons have their long axis oriented along a single [110] direction of the semiconductor substrate. 2. The graphene nanoribbon array of claim 1 , wherein at least 80 percent of the graphene nanoribbons have their long axis oriented along a single [110] direction of the semiconductor substrate. 3. The graphene nanoribbon array of claim 1 , wherein the at least 60 percent of the graphene nanoribbons have their long axes rotated by no more than ±15° from the [110] direction of the semiconductor substrate. 4. The graphene nanoribbon array of claim 1 , wherein the at least 80 percent of the graphene nanoribbons have their long axes rotated by no more than ±5° from the [110] direction of the semiconductor substrate. 5. The graphene nanoribbon array of claim 1 , wherein the semiconductor substrate having a (001) facet is a germanium substrate. 6. The graphene nanoribbon array of claim 1 , wherein the semiconductor substrate having a (001) facet is a semiconductor substrate. 7. The array of claim 1 , wherein the graphene nanoribbons having their long axes oriented along a single [110] direction of the semiconductor are arranged in a regular pattern. 8. The array of claim 1 , wherein the average width of the graphene nanoribbons in the array is no greater than 50 nm. 9. The array of claim 8 , wherein the graphene nanoribbons having their long axes oriented along a single [110] direction of the semiconductor have a lateral spacing of no greater than 50 nm. 10. The array of claim 1 , wherein the plurality of graphene nanoribbons comprises graphene nanoribbons having edges with an rms roughness of 1 nm or lower over edge lengths of at least 40 nm. 11. The array of claim 1 comprising at least 1000 of the graphene nanoribbons. 12. The array of claim 1 , wherein the graphene nanoribbons do not comprise heterogeneous nucleation sites along their lengths. 13. The array of claim 1 comprising at least 1000 of the graphene nanoribbons, the graphene nanoribbons having an average width of no greater than 10 nm and a lateral spacing of no greater than 10 nm, wherein the graphene nanoribbons having their long axes oriented along a single [110] direction of the semiconductor are arranged in a regular pattern. 14. A graphene nanoribbon array comprising: a semiconductor substrate having a (001) facet; and a plurality of graphene nanoribbons on the (001) facet of the semiconductor substrate, each of the graphene nanoribbons comprising an amorphous carbon seed along its length; wherein the graphene nanoribbons have aspect ratios of at least 4; and wherein the graphene nanoribbons have the armchair crystallographic direction of graphene running all the way along their long axes with an armchair configuration along their edges; and further wherein the graphene nanoribbons have their long axes oriented along a [110] direction of the semiconductor. 15. A method of growing graphene nanoribbons, the method comprising: forming an array of graphene seeds on the (001) facet of a semiconductor substrate, wherein a majority of the graphene seeds have a single crystallographic orientation; and growing graphene nanoribbons from the graphene seeds via chemical vapor deposition from a mixture of methane gas and hydrogen gas, wherein the partial pressures of the methane and hydrogen are selected to result in the growth of graphene nanoribbons having their long axes oriented along a [110] direction of the semiconductor substrate and their armchair edges running parallel with the [110] direction of the semiconductor substrate. 16. The method of claim 15 , wherein at least 60% of the graphene nanoribbons are oriented along the same [110] direction of the semiconductor substrate. 17. The method of claim 15 , wherein the step of forming an array of graphene seeds on the (001) facet of a semiconductor substrate comprises: growing a sheet of monolayer graphene on a surface of a sheet-growth substrate; transferring the sheet of monolayer graphene onto a (001) facet of a semiconductor substrate; and patterning an array of graphene seeds into the sheet of monolayer graphene and removing the remainder of the sheet of monolayer graphene. 18. The method of claim 17 , wherein the surface of the sheet-growth substrate is the (111) facet of a copper substrate. 19. The method of claim 15 , wherein the graphene nanoribbons have an average width of no greater than about 10 nm. 20. The method of claim 15 , further comprising incorporating the graphene nanoribbons and the semiconductor substrate into an electronic or photonic device. 21. The method of claim 15 , further comprising releasing at least a portion of the graphene nanoribbons from the semiconductor substrate and transferring the released graphene nanoribbons to a second substrate.
used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title
Wafer tapes, e.g. grinding or dicing support tapes · CPC title
using temporarily an auxiliary support · CPC title
Crystal orientation · CPC title
Microstructure · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.