Array substrate, manufacturing method thereof and display device

Patent metadata

Field	Value
Publication number	US-9761615-B2
Application number	US-201414769658-A
Country	US
Kind code	B2
Filing date	Oct 27, 2014
Priority date	Aug 21, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises: a base substrate ( 1 ), thin-film transistors (TFTs), an isolation layer ( 10 ) and an organic resin layer ( 8 ) formed on the base substrate ( 1 ), and a common electrode layer ( 12 ) formed on the organic resin layer ( 8 ). The isolation layer ( 10 ) covers source electrodes ( 6 ) and drain electrodes ( 7 ) of the TFTs; the organic resin layer ( 8 ) covers the isolation layer ( 10 ) and is provided with first through holes ( 9 ) corresponding to the drain electrodes ( 7 ) of the TFTs; the isolation layer ( 10 ) is provided with second through holes ( 11 ) communicated with the first through holes ( 9 ) to expose partial drain electrodes ( 7 ); and the dimension of the second through holes ( 11 ) is greater than that of the first through holes ( 9 ). The array substrate, the manufacturing method thereof and the display device resolve the problem of forming dark dots, ensure the product quality, reduce the waste of production materials, and reduce the production cost.

First claim

The invention claimed is:

1. An array substrate, comprising: a base substrate, thin-film transistors (TFTs), an isolation layer and an organic resin layer formed on the base substrate, and a common electrode layer formed on the organic resin layer, wherein
the isolation layer covers source electrodes and drain electrodes of the TFTs; the organic resin layer covers the isolation layer and are provided with first through holes corresponding to the drain electrodes of the TFTs;
the isolation layer is provided with second through holes communicated with the first through holes to expose partial drain electrodes; and
the dimension of the second through holes is greater than that of the first through holes;
an acute angle is formed between a lower surface of the organic resin layer and a boundary of the isolation layer contacting the second through holes.

2. The array substrate according to claim 1 , wherein a thickness of the isolation layer is greater than that of the common electrode layer.

3. The array substrate according to claim 1 , further comprising a passivation layer and a pixel electrode layer, wherein
the passivation layer is disposed on the common electrode layer and covers the common electrode layer; and
the pixel electrode layer is disposed on the passivation layer.

4. The array substrate according to claim 3 , wherein the common electrode layer is also disposed at positions of the second through holes; parts of the common electrode layer disposed on the drain electrodes are not connected with parts of the common electrode layer disposed on the organic resin layer; and
the passivation layer is connected with the isolation layer at the second through holes.

5. A display device, comprising the array substrate according to claim 1 .

6. The array substrate according to claim 2 , further comprising a passivation layer and a pixel electrode layer, wherein
the passivation layer is disposed on the common electrode layer and covers the common electrode layer; and
the pixel electrode layer is disposed on the passivation layer.

7. The array substrate according to claim 6 , wherein the common electrode layer is also disposed at positions of the second through holes; parts of the common electrode layer disposed on the drain electrodes are not connected with parts of the common electrode layer disposed on the organic resin layer; and
the passivation layer is connected with the isolation layer at the second through holes.

8. The array substrate according to claim 1 , further comprising a passivation layer and a pixel electrode layer, wherein
the passivation layer is disposed on the common electrode layer and covers the common electrode layer; and
the pixel electrode layer is disposed on the passivation layer.

9. The array substrate according to claim 8 , wherein the common electrode layer is also disposed at positions of the second through holes; parts of the common electrode layer disposed on the drain electrodes are not connected with parts of the common electrode layer disposed on the organic resin layer; and
the passivation layer is connected with the isolation layer at the second through holes.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Jiang Xiaohui
• Yan Changjiang
• Zhang Jiaxiang

Classifications

• H10P50/287

  by chemical means · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• Y02P80/30

  Reducing waste in manufacturing processes; Calculations of released waste quantities · CPC title