Layout of transmission vias for memory device

Patent metadata

Field	Value
Publication number	US-9761564-B1
Application number	US-201615198647-A
Country	US
Kind code	B1
Filing date	Jun 30, 2016
Priority date	Jun 30, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate;
first, second and third memory cell arrays arranged in a first direction in the substrate;
a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes;
a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes; and
a first voltage generator arranged between the first memory cell array and the second memory cell array to coupled to the first and second electrodes, the first voltage generator being configured to generate a first voltage between a ground voltage and a power supply voltage.

2. The apparatus of claim 1 , wherein the first and second through electrodes are arranged in line in a second direction substantially perpendicular to the first direction, and the third and fourth through electrodes are arranged in the second direction.

3. The apparatus of claim 1 , wherein the first through electrode is supplied with the ground voltage and the second through electrode is supplied with the power supply voltage.

4. The apparatus of claim 1 , wherein the first set of through electrodes further includes fifth and sixth through electrodes, and wherein the apparatus further comprises a second voltage generator arranged between the first and second memory cell arrays and coupled to the fifth and sixth through electrodes, the second voltage generator being configured to generate a second voltage independently of the first voltage.

5. The apparatus of claim 4 , wherein the third through electrode is supplied with the ground voltage and the fourth through electrode is supplied with the power supply voltage, and wherein the apparatus further comprises a third voltage generator arranged between the second and third memory cell arrays and coupled to the third and fourth through electrodes, the third voltage generator being configured to generate a third voltage equal to the first voltage.

6. An apparatus comprising:
a first chip extending on a first plane defined by a first direction and a second direction that is perpendicular to the first direction, the first chip comprising:
a substrate;
a first memory cell array and a second memory cell array arranged in the first direction on the substrate;
a first area disposed between the first memory cell array and the second memory cell array, the first area aligned to the first memory cell array along the first direction,
one or more first through electrodes disposed in the first area;
a second area disposed adjacent to the first memory cell array and aligned to the first memory cell array along a third direction opposite to the first direction; and
one or more second through electrodes disposed in the second area.

7. The apparatus of claim 6 , further comprising:
a third area disposed adjacent to the second memory cell array and aligned to the second memory cell array along the first direction; and
one or more third through electrodes disposed in the third area.

8. The apparatus of claim 7 , wherein the second area and the third area are symmetrically spaced with respect to the first area.

9. The apparatus of claim 7 , wherein a first distance between the first area and the second area and a second distance between the first area and the third area are substantially the same.

10. The apparatus of claim 7 , wherein a number of the one or more second through substrates and a number of the one or more third substrates are substantially the same.

11. The apparatus of claim 6 , further comprising:
one or more circuits on the substrate;
one or more first voltage generators configured to supply a first voltage to the one or more circuits,
wherein the one or more first voltage generators are disposed on the first area and the second area.

12. The apparatus of claim 7 , further comprising:
one or more circuits on the substrate;
one or more first voltage generators configured to supply a first voltage to the one or more circuits,
one or more first sense amplifiers coupled to the first memory cell array;
one or more second sense amplifiers coupled to the second memory cell array; and
one or more second voltage generators configured to supply a second voltage,
wherein a first portion of the one or more second voltage generators are disposed on the second area and configured to supply the second voltage to the one or more first sense amplifiers, and
wherein a second portion of the one or more second voltage generators are disposed on the third area and configured to supply the second voltage to the one or more second sense amplifiers.

13. The apparatus of claim 6 , further comprising:
a second chip having the first chip stacked thereon in a fourth direction perpendicular to the first direction and the second direction, the second chip comprising:
a second substrate;
a fourth area corresponding to the first area;
one or more fourth through electrodes disposed in the fourth area;
one or more first terminals configured to couple the one or more fourth through electrodes to the one or more first through electrodes in series along the fourth direction;
a fifth area corresponding to the first area;
one or more fifth through electrodes disposed in the fifth area; and
one or more second terminals configured to couple the one or more fifth through electrodes to the one or more second through electrodes in series along the fourth direction.

14. An apparatus including:
an interposer comprising one or more power lines configured to supply a power supply voltage;
at least one core chip extending on a first plane defined by a first direction and a second direction that is perpendicular to the first direction, the at least one core chip comprising:
a first substrate;
a first memory cell array on the first substrate;
one or more first through electrodes aligned to the first memory cell array along the first direction; and
one or more second through electrodes aligned to the first memory cell array along a third direction opposite to the first direction;

an interface chip having the at least one core chip stacked thereon in a fourth direction perpendicular to the first direction and the second direction, the interface chip comprising:
a second substrate;
one or more third through electrodes corresponding to the one or more first through electrodes;
one or more first terminals configured to couple the one or more third through electrodes to the one or more first through electrodes in series along the fourth direction;
one or more fourth through electrodes corresponding to the one or more second through electrodes; and
one or more second terminals configured to couple the one or more fourth through electrodes to the one or more second through electrodes in series along the fourth direction; and

one or more first interconnects configured to couple the one or more power lines to the one or more third through electrodes and the one or more fourth through electrodes.

15. The apparatus of claim 14 , further comprising:
one or more circuits on the first substrate;
one or more first voltage generators configured to supply a first voltage to the one or more circuits,
wherein the one or more first voltage generators are disposed adjacent to the one or more first through electrodes.

16. T

Assignees

• Micron Technology Inc

Inventors

• Shibata Kayoko

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title