Chip package and method for forming the same

Patent metadata

Field	Value
Publication number	US-9761510-B2
Application number	US-201514706896-A
Country	US
Kind code	B2
Filing date	May 7, 2015
Priority date	May 9, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.

First claim

What is claimed is:

1. A chip package, comprising:
a first device substrate attached to a first surface of a second device substrate;
a third device substrate attached to a second surface of the second device substrate opposite to the first surface;
an insulating layer covering the first, second and third device substrates and having at least one opening therein;
at least one first bump disposed under a bottom of the at least one opening;
a redistribution layer disposed on the insulating layer and electrically connected to the at least one first bump through the at least one opening; and
a third bump surrounded by the insulating layer, wherein the redistribution layer continuously extends on the third bump and into the at least one opening, wherein the third bump is located on the third device substrate and electrically connected to a third bonding pad in the third device substrate, and the third bump is a bonding ball and has a flat upper surface, and wherein the redistribution layer on the insulating layer covers the third bump and is electrically connected thereto.

2. The chip package as claimed in claim 1 , wherein a size of the second device substrate is greater than that of the third device substrate and less than that of the first device substrate.

3. The chip package as claimed in claim 1 , wherein the at least one first bump is located on the first device substrate and is electrically connected to a first bonding pad in the first device substrate.

4. The chip package as claimed in claim 1 , wherein the at least one first bump is located on the second device substrate and is electrically connected to a second bonding pad in the second device substrate.

5. The chip package as claimed in claim 1 , comprising a plurality of first bumps and a plurality of openings in the insulating layer, wherein the plurality of first bumps is correspondingly disposed under bottoms of the openings, and wherein one of the plurality of first bumps is located on the first device substrate and is electrically connected to a first bonding pad in the first device substrate, and an another one of the plurality of first bumps is located on the second device substrate and is electrically connected to a second bonding pad in the second device substrate.

6. The chip package as claimed in claim 1 , further comprising a plurality of conducting structures disposed in the insulating layer, wherein the plurality of conducting structures electrically connect a first conducting pad in the first device substrate to a second conducting pad in the second device substrate and electrically connect an another first conducting pad in the first device substrate to a third conducting pad in the third device substrate.

7. The chip package as claimed in claim 1 , further comprising a plurality of conducting structures disposed in the insulating layer, wherein the plurality of conducting structures electrically connect a first conducting pad in the first device substrate to a second conducting pad in the second device substrate, electrically connect an another first conducting pad in the first device substrate to a third conducting pad in the third device substrate, and electrically connect an another second conducting pad in the second device substrate to an another third conducting pad in the third device substrate.

8. The chip package as claimed in claim 1 , further comprising a second bump located on the redistribution layer on the insulating layer.

9. The chip package as claimed in claim 8 , wherein a material of the second bump is different from that of the at least one first bump.

10. The chip package as claimed in claim 8 , wherein the at least one first bump and the second bump are bonding balls, and a size of the second bump is greater than that of the at least one first bump.

11. The chip package as claimed in claim 1 , further comprising:
a fourth bump disposed between the first device substrate and the redistribution layer; and
an another redistribution layer disposed on the insulating layer and electrically connected to the fourth bump.

12. The chip package as claimed in claim 11 , further comprising a second bump located on the another redistribution layer, wherein a material of the second bump is different from that of the third bump, the fourth bump and the at least one first bump.

13. The chip package as claimed in claim 11 , further comprising a second bump located on the another redistribution layer, wherein the second, third and fourth bumps are bonding balls, and a size of the second bump is greater than that of the third and fourth bumps.

14. The chip package as claimed in claim 11 , wherein the fourth bump is located on the third device substrate and is electrically connected to an another third bonding pad in the third device substrate, and wherein the chip package further comprises an another insulating layer covering the insulating layer and the redistribution layer and having an opening exposing the fourth bump, and the another redistribution layer is electrically connected to the fourth bump through the opening in the another insulating layer.

15. The chip package as claimed in claim 14 , wherein the fourth bump is a bonding ball and has a flat upper surface.

16. The chip package as claimed in claim 11 , wherein the fourth bump is electrically connected a first conducting pad in the first device substrate or a second conducting pad in the second device substrate, and wherein the insulating layer has a plurality of openings, and the another redistribution layer is electrically connected to the fourth bump through one of the plurality of openings which exposes the fourth bump.

17. A method for forming a chip package, comprising:
attaching a first device substrate to a first surface of a second device substrate;
attaching a third device substrate to a second surface of the second device substrate opposite to the first surface;
forming at least one first bump and an insulating layer, wherein the insulating layer covers the first, second and third device substrates and has at least one opening therein, such that the at least one first bump is formed under a bottom of the at least one opening;
forming a redistribution layer on the insulating layer, wherein the redistribution layer is electrically connected to the at least one first bump through the at least one opening; and
forming a third bump surrounded by the insulating layer, wherein the redistribution layer continuously extends on the third bump and into the at least one opening, wherein the third bump is located on the third device substrate and electrically connected to a third bonding pad in the third device substrate, and the third bump is a bonding ball and has a flat upper surface, and wherein the redistribution layer on the insulating layer covers the third bump and is electrically connected thereto.

18. The method as claimed in claim 17 , wherein a size of the second device substrate is greater than that of the third device substrate and less than that of the first device substrate.

19. The method as claimed in claim 17 , wherein the at least one first bump is located on the first device substrate and is electrically connected to a first bonding pad in the first device substrate.

20. The method as claimed in claim 17 , wherein the at least one first bump is located on the second device substrate and is electrically connected to a second bonding pad in the second device substrate.

21. The method as claimed in claim 17 , comprising forming a plurality o

Assignees

• Xintec Inc

Inventors

• Liu Chien-Hung

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title