Semiconductor structure and method of forming the same

Patent metadata

Field	Value
Publication number	US-9761494-B2
Application number	US-201213465885-A
Country	US
Kind code	B2
Filing date	May 7, 2012
Priority date	May 7, 2012
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The at least one lightly doped region has a first conductivity type. A source feature and a drain feature are on opposite sides of the gate structure in the substrate. The source feature and the drain feature have the first conductivity type. The source feature is in the at least one lightly doped region. A bulk pick-up region adjoins the source feature in the at least one lightly doped region. The bulk pick-up region has a second conductivity type.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first gate structure disposed on a substrate;
at least one lightly doped region, at least a portion of the at least one lightly doped region having a first conductivity type adjoining the first gate structure in the substrate;
a source feature and a drain feature having the first conductivity type on opposite sides of the first gate structure in the substrate, wherein a top surface of the source feature is aligned with a top surface of the lightly doped region;
a first bulk pick-up region having a second conductivity type adjoining the source feature in the at least one lightly doped region;
a salicide layer on the source feature and the first bulk pick-up region, the salicide layer extends into the substrate to a depth D S , and the depth D S is larger than a depth D L of the at least one lightly doped region; and
a well region in the substrate, wherein the well region has the second conductivity type,
wherein the at least one lightly doped region, the source feature and the first bulk pick-up region are within the well region.

2. The semiconductor structure of claim 1 , further comprising a second bulk pick-up region adjoining the source feature and opposite to the first bulk pick-up region.

3. The semiconductor structure of claim 2 , wherein the first bulk pick-up region and the second bulk pick-up region are separated by a distance W in a range from about 0.2 μm to about 10 μm.

4. The semiconductor structure of claim 1 , wherein the first bulk pick-up region comprises boron in a dosage range from about 1E15 to 5E15/cm 2 .

5. The semiconductor structure of claim 1 , further comprising a contact plug disposed on the salicide layer.

6. The semiconductor structure of claim 1 , further comprising a second gate structure adjacent to the first gate structure, wherein the second gate structure shares the source feature and the first bulk pick-up region of the first gate structure.

7. The semiconductor structure of claim 6 , wherein the salicide layer covers an entirety of an upper-most surface of the first bulk pick-up region exposed between spacers on sidewalls of the first gate structure and the second gate structure.

8. The semiconductor structure of claim 1 further comprising spacers on sidewalls of the first gate structure covering a portion of the at least one lightly doped region, wherein a current path is from the drain feature, underneath the first gate structure, along the covered lightly doped region to the source feature.

9. The semiconductor structure of claim 1 , further comprising a spacer on a sidewall of the first gate structure, wherein a sidewall of the first bulk pick-up region extends underneath the spacer.

10. The semiconductor structure of claim 1 , wherein a top surface of the salicide layer is coplanar with a top surface of the at least one lightly doped region.

11. A semiconductor structure comprising:
a first gate structure and a second adjacent gate structure disposed on a substrate, wherein the first gate structure is separated from the second adjacent gate structure in a first direction parallel to a top surface of the substrate;
a well region disposed in the substrate between the first gate structure and the second gate structure, the well region having a first conductivity type;
a lightly doped region disposed in the well region, the lightly doped region having a second conductivity type;
a heavily doped region disposed in the lightly doped region, the heavily doped region having the second conductivity type;
a first bulk pick-up region adjoining the heavily doped region, the first bulk pick-up region having the first conductivity type; and
a salicide layer on the heavily doped region and the first bulk pick-up region, the salicide layer extends into the substrate to a depth D S , and the depth D S is larger than a depth D L of the lightly doped region,
wherein sidewalls of the first bulk pick-up region are aligned with sidewalls of the heavily doped region in a second direction parallel to the top surface of the substrate and perpendicular to the first direction,
wherein the lightly doped region, the heavily doped region and the first bulk pick-up region are within the well region.

12. The semiconductor structure of claim 11 , further comprising a second bulk pick-up region in the lightly doped region, wherein the heavily doped region is between the first bulk pick-up region and the second bulk pick-up region.

13. The semiconductor structure of claim 12 , wherein the first bulk pick-up region and the second bulk pick-up region are separated by a distance W in a range from about 0.2 μm to about 10 μm.

14. The semiconductor structure of claim 11 , wherein the first bulk pick-up region comprises boron in a dosage range from about 1E15 to 5E15/cm 2 .

15. The semiconductor structure of claim 11 , further comprising a contact plug disposed on the salicide layer.

16. A semiconductor structure comprising:
a first gate structure and an adjacent second gate structure disposed on a substrate;
a well region disposed in the substrate between the first gate structure and the second gate structure, the well region having a first conductivity type;
a lightly doped region disposed in the well region, the lightly doped region having a second conductivity type;
a first heavily doped region disposed in the lightly doped region, the first heavily doped region having the second conductivity type, wherein a top surface of the first heavily doped region is aligned with a top surface of the lightly doped region;
a source feature and a drain feature on opposite sides of the first gate structure in the substrate, wherein a top surface of the source feature is aligned with a top surface of the lightly doped region;
an isolation feature in the substrate, wherein at least one of the first gate structure or the second gate structure overlies the isolation feature;
a first bulk pick-up region adjoining the first heavily doped region in the lightly doped region, the first bulk pick-up region having the first conductivity type;
a salicide layer on the source feature and the first bulk pick-up region, the salicide layer extends into the substrate to a depth D S , and the depth D S is larger than a depth D L of the lightly doped region, wherein a top surface of the salicide layer is coplanar with a top surface of the lightly doped region; and further
wherein the lightly doped region, the source feature and the first bulk pick-up region are within the well region.

17. The semiconductor structure of claim 16 , wherein the isolation feature is positioned between at least one of the first gate structure or the second gate structure and a second heavily doped region disposed in the substrate.

18. The semiconductor structure of claim 16 , wherein the first gate structure is separated from the second adjacent gate structure in a first direction parallel to a top surface of the substrate, and sidewalls of the first bulk pick-up region are aligned with sidewalls of the first heavily doped region in a second direction parallel to the top surface of the substrate and perpendicular to the first direction.

Assignees

• Chen Po-Yu
• Huang Wan-Hua
• Chen Jing-Ying
• Wu Kuo-Ming
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Po-Yu
• Huang Wan-Hua
• Chen Jing-Ying
• Wu Kuo-Ming

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H01L29/0603

  Electricity · mapped topic

• H01L21/823475

  Electricity · mapped topic

• H01L21/76895

  Electricity · mapped topic

• H01L21/823425 Primary

  Electricity · mapped topic