Wafer carrier

US9761470B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9761470-B2
Application numberUS-201514699235-A
CountryUS
Kind codeB2
Filing dateApr 29, 2015
Priority dateMay 8, 2014
Publication dateSep 12, 2017
Grant dateSep 12, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A wafer carrier 1 includes a lower unit 2 on which a semiconductor wafer 100 is placed, and an upper unit 3 detachably attached to the lower unit 2 , and forming a sealed chamber 4 for housing the semiconductor wafer 100 between the upper unit 3 and the lower unit 2 . The upper unit 3 is provided with plural lock mechanisms 5 that fix the lower unit 2 to the upper unit 3 by abutting on a side surface of the lower unit 2.

First claim

Opening claim text (preview).

What is claimed is: 1. A wafer carrier comprising: a lower unit of which a semiconductor wafer is placed, wherein the lower unit comprises a lower surface that meets a side surface that is substantially perpendicular to the lower surface; and an upper unit detachably attached to the lower unit, and forming a sealed chamber for housing the semiconductor wafer between the upper unit and the lower unit, wherein concave portions are formed in the side surface of the lower unit, the upper unit is provided with plural lock mechanisms that fix the lower unit to the upper unit, the plural lock mechanisms abut on the side surface of the lower unit in the concave portions, each lock mechanism includes a spherical body fitted to the concave portion of the lower unit, a lock lever provided in the upper unit so as to swing, wherein the lock lever includes a tip portion of which abuts on the spherical body to press the spherical body to the concave portion side of the lower unit and a spring member that biases the tip portion of the lock lever to the spherical body side, and the spherical body of respective lock mechanisms abut on the side surface of the lower unit, and a lowermost part of the spherical body is positioned above a plane formed by the lower surface of the lower unit in a direction of the upper unit. 2. The wafer carrier according to claim 1 , wherein a through hole formed in a swinging direction of the lock lever of the lock mechanism is formed in the upper unit, and the spherical body is provided so as to reciprocate in the through hole, and a convex portion protruding to a central side of the through hole and inclined to the lock lever is formed at an end portion of the sealed chamber side inside the through hole. 3. The wafer carrier according to claim 1 , wherein the upper unit is provided with a guide member that guides extension and contraction of the spring member in the direction of the spherical body. 4. The wafer carrier according to claim 1 , wherein the lock mechanisms are built in the upper unit. 5. The wafer carrier according to claim 1 , wherein the spherical body is made of a metal, and the lock lever is made of a resin. 6. The wafer carrier according to claim 1 , wherein plural lug portions having different shapes from each other and protruding outward are formed in the side surface of the lower unit, the concave portions are formed in side surfaces of the lug portions, and concave positioning portions are respectively formed in the upper unit so as to correspond to the lug portions of the lower unit.

Assignees

Inventors

Classifications

  • characterised by sealing arrangements · CPC title

  • characterised by locking systems · CPC title

  • specially adapted for a single substrate · CPC title

  • characterised by the construction of the processing chambers, e.g. modular processing chambers · CPC title

  • H10P72/12Primary

    Vertical boat type carrier whereby the substrates are horizontally supported, e.g. comprising rod-shaped elements · CPC title

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Frequently asked questions

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What does patent US9761470B2 cover?
A wafer carrier 1 includes a lower unit 2 on which a semiconductor wafer 100 is placed, and an upper unit 3 detachably attached to the lower unit 2 , and forming a sealed chamber 4 for housing the semiconductor wafer 100 between the upper unit 3 and the lower unit 2 . The upper unit 3 is provided with plural lock mechanisms 5 that fix the lower unit 2 to the upper unit 3 …
Who is the assignee on this patent?
Toyota Motor Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P72/0462. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).