Piezoelectric and logic integrated delay line memory

Patent metadata

Field	Value
Publication number	US-9761324-B2
Application number	US-201515116441-A
Country	US
Kind code	B2
Filing date	Feb 3, 2015
Priority date	Feb 3, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Delay line memory device, systems and methods are disclosed. In one aspect, a delay line memory device includes a substrate; an electronic unit disposed on the substrate and operable to receive, amplify, and/or synchronize data signals into a bit stream to be transmitted as acoustic pulses carrying data stored in the delay line memory device; a first and a second piezoelectric transducer disposed on the substrate and in communication with the electronic unit, in which the first piezoelectric transducer is operable to transmit the data signals to the acoustic pulses that carry the data through the bulk of the substrate, and the second piezoelectric transducer is operable to transduce the received acoustic pulses to intermediate electrical signals containing the data, which are transferred to the electronic unit via an electrical interconnect to cause refresh of the data in the delay line memory device.

First claim

What is claimed is:

1. A delay line memory device, comprising:
a substrate;
a first electronic unit and a second electronic unit disposed on a first side and a second side of the substrate, respectively, wherein the first electronic unit is operable to receive, amplify, and/or synchronize data signals into a bit stream to be transmitted as acoustic pulses carrying data stored in the delay line memory device;
a first piezoelectric transducer and a second piezoelectric transducer disposed on the first and second sides of the substrate, respectively, such that the first piezoelectric transducer is in communication with the first electronic unit, and the second piezoelectric transducer is in communication with the second electronic unit, wherein the first piezoelectric transducer is operable to transduce and transmit the bit stream of the data signals received from the first electronic unit to the acoustic pulses that carry the data through the bulk of the substrate, and the second piezoelectric transducer is operable to receive and transduce the transmitted acoustic pulses to intermediate electrical signals containing the data to be received by the second electronic unit; and
an electrical interconnect that electrically connects the first and second electronic units across the first and second sides of the substrate to transfer the intermediate electrical signals containing the data between the second electronic unit and the first electronic unit.

2. The device of claim 1 , wherein the substrate includes silicon.

3. The device of claim 2 , wherein the substrate is a silicon die.

4. The device of claim 1 , wherein the electronic units include a circuit or one or more microchips.

5. The device of claim 1 , wherein the piezoelectric transducers include piezoelectric thin films including at least one of aluminum nitride (AlN), zinc oxide (ZnO), or polyvinylidene fluoride (PVDF).

6. The device of claim 5 , wherein one or both of the first electronic unit and the second electronic unit include a CMOS device.

7. The device of claim 1 , wherein the delay line memory device is interfaced with an integrated circuit device such that the first electronic unit is in communication with the integrated circuit device to receive the data signals to be stored in the delay line memory device.

8. The device of claim 7 , wherein the integrated circuit device includes a processor, a sensor, or a signal conditioning circuit.

9. The device of claim 7 , wherein the delay line memory device is operable to convolve or process incoming data from the integrated circuit device with the data to be refreshed by the delay line memory device.

10. The device of claim 1 , wherein the data signals include electrical pulse signals or radio frequency (RF) pulse signals.

11. The device of claim 1 , wherein the data signals include a frequency in a range of 1 to 10 GHz.

12. The device of claim 1 , wherein the acoustic pulses travel through the bulk of the substrate at substantially the speed of sound into the bulk of the substrate.

13. The device of claim 1 , wherein the intermediate electrical signals travel through the electrical interconnect at a speed near that of the speed of light.

14. The device of claim 1 , further comprising:
an array of the first electronic units disposed on the first side of the substrate, and an array of the second electronic units disposed on the second side of the substrate;
an array of the electrical interconnects that electrically connect corresponding first and second electronic units of their respective arrays; and
an array of the first piezoelectric transducers disposed on the first side of the substrate such that the first piezoelectric transducers are in communication with corresponding first electronic units of their respective arrays, and an array of the second piezoelectric transducers disposed on the second side of the substrate such that the second piezoelectric transducers are in communication with corresponding second electronic units of their respective arrays.

15. A delay line memory chip device, comprising:
a substrate; and
a first acoustic communication unit and a second acoustic communication unit disposed on a first side and a second side of the substrate, respectively, wherein the first and second acoustic communication units each include an electronic component coupled between a transmit piezoelectric transducer and a receive piezoelectric transducer,
wherein the electronic unit of the first acoustic communication unit is operable to receive, amplify, and/or synchronize data signals into a bit stream to be transmitted as acoustic pulses carrying data stored in the delay line memory device,
wherein the transmit piezoelectric transducer of the first communication unit is operable to transduce and transmit the bit stream of the data signals received from the electronic unit of the first acoustic communication unit to the acoustic pulses that carry the data through a first portion in the bulk of the substrate to be received by the receive piezoelectric transducer of the second communication unit, wherein the receive piezoelectric transducer of the second transducer is operable to transduce the received acoustic pulses to intermediate signals containing the data,
wherein the electronic unit of the second acoustic communication unit is operable to receive and amplify the intermediate signals to be transmitted as return acoustic pulses carrying the data to the first acoustic communication unit,
wherein the transmit piezoelectric transducer of the second communication unit is operable to transduce and transmit the intermediate signals received from the electronic unit of the second acoustic communication unit to the return acoustic pulses that contain the data through a second portion in the bulk of the substrate to be received by the receive piezoelectric transducer of the first communication unit.

16. The device of claim 15 , wherein the substrate includes silicon.

17. The device of claim 16 , wherein the substrate is a silicon die.

18. The device of claim 15 , wherein the electronic units include a circuit or one or more microchips.

19. The device of claim 15 , wherein the transmit and the receive piezoelectric transducers include piezoelectric thin films including at least one of aluminum nitride (AlN), zinc oxide (ZnO), or polyvinylidene fluoride (PVDF).

20. The device of claim 19 , wherein one or both of the electronic units of the first and the second acoustic communication unit include a CMOS device.

21. The device of claim 15 , wherein the delay line memory device is interfaced with an integrated circuit device such that the electronic unit of the first acoustic communication unit is in communication with the integrated circuit device to receive the data signals to be stored in the delay line memory device.

22. The device of claim 21 , wherein the integrated circuit device includes a processor, a sensor, or a signal conditioning circuit.

23. The device of claim 15 , wherein the data signals include electrical pulse signals or radio frequency (RF) pulse signals.

24. The device of claim 15 , further comprising:
an array of the first acoustic communication units disposed on the first side of the substrate, and an array of the second acoustic communication units disposed on the second side of the substrate.

25. A method to store data in a delay line memory, comprising:
receiving, at an electronics unit o

Assignees

• Univ Cornell

Inventors

• Lal Amit
• Kuo Justin C

Classifications

• G11C7/16 Primary

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• B06B2201/20

  Application to multi-element transducer · CPC title

• B06B2201/70

  Specific application · CPC title

• B06B1/0215

  for generating pulses, e.g. bursts of oscillations, envelopes · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title