Semiconductor storage device

Patent metadata

Field	Value
Publication number	US-9761293-B2
Application number	US-201615261832-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Mar 12, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

According to one embodiment, a semiconductor storage device includes a first semiconductor storage area; a second semiconductor storage area; a reference circuit; a sense amplifier senses data stored in the first semiconductor storage area and the second semiconductor storage area; and a control circuit.

First claim

What is claimed is:

1. A semiconductor storage device comprising:
a first semiconductor storage area;
a second semiconductor storage area;
a reference circuit;
a sense amplifier which senses data stored in the first semiconductor storage area and the second semiconductor storage area;
a control circuit; and
a storage module which stores first sense information relating to a first operation mode and second sense information relating to a second operation mode, and supplies the first sense information to the control circuit, when receiving a first operation mode selection signal which selects the first operation mode, or supplies the second sense information to the control circuit, when receiving a second operation mode selection signal which selects the second operation mode,
wherein:
the data stored in the first semiconductor storage area or the second semiconductor storage area is sensed in the first operation mode by using the reference circuit,
the data stored in the first semiconductor storage area is sensed in the second operation mode by using the second semiconductor storage area,
the control circuit supplies a first control signal to the sense amplifier when the first operation mode selection signal and the first sense information are received, and supplies a second control signal to the sense amplifier when the second operation mode selection signal and the second sense information are received,
the sense amplifier electrically connects the reference circuit and the first semiconductor storage area or the reference circuit and the second semiconductor storage area, when receiving the first operation mode selection signal and the first control signal, and to executes a sense operation of sensing the data stored in the first semiconductor storage area or the second semiconductor storage area by using the reference circuit, and
the sense amplifier electrically connects the first semiconductor storage area and the second semiconductor storage area, when receiving the second operation mode selection signal and the second control signal, and executes a sense operation of sensing the data stored in the first semiconductor storage area by using the second semiconductor storage area.

2. The device of claim 1 , wherein:
the first sense information includes a first sense period indicative of a period which is needed for a first sense operation in which the sense amplifier senses data in the first operation mode, and a first read period indicative of a period which is needed from a start of the first sense operation by the sense amplifier until read of the data, and
the second sense information includes a second sense period indicative of a period which is needed for a second sense operation in which the sense amplifier senses data in the second operation mode, and a second read period indicative of a period which is needed from a start of the second sense operation by the sense amplifier until read of the data.

3. The device of claim 2 , wherein:
the first control signal includes a first start signal for starting the first sense operation, a first termination signal for terminating the first sense operation, and a first output signal for causing the sense amplifier to output a result of the first sense operation, and
the second control signal includes a second start signal, a second termination signal for terminating the second sense operation, and a second output signal for causing the sense amplifier to output a result of the second sense operation.

4. The device of claim 3 , wherein the control circuit determines the first termination signal, based on the first operation mode selection signal and the first sense period, determines the first output signal, based on the first operation mode selection signal and the first read period, determines the second termination signal, based on the second operation mode selection signal and the second sense period, and determines the second output signal, based on the second operation mode selection signal and the second read period.

5. The device of claim 2 , wherein the first sense period in the first operation mode is longer than the second sense period in the second operation mode.

6. The device of claim 2 , wherein the first read period in the first operation mode is longer than the second read period in the second operation mode.

7. The device of claim 1 , wherein the sense amplifier includes a switch circuit which electrically connects the reference circuit and the first semiconductor storage area or the second semiconductor storage area, when receiving the first operation mode selection signal, and which electrically connects the first semiconductor storage area and the second semiconductor storage area, when receiving the second operation mode selection signal.

8. The device of claim 1 , wherein, at a time of the second operation mode, the first semiconductor storage area and the second semiconductor storage area store mutually complementary data.

9. The device of claim 1 , wherein, in a case of selecting the first operation mode and then selecting the second operation mode, or in a case of selecting the second operation mode and then selecting the first operation mode, the control circuit initializes the first semiconductor storage area and the second semiconductor storage area.

10. The device of claim 1 , wherein each of the first semiconductor storage area and the second semiconductor storage area includes a plurality of memory cells.

11. The device of claim 10 , wherein the first semiconductor storage area and the second semiconductor storage area include the same number of said memory cells.

12. The device of claim 10 , wherein the memory cell includes a magnetoresistive element.

13. The device of claim 10 , wherein the memory cell is any one of an MRAM (Magnetic Random Access Memory), an FeRAM (Ferroelectric random access memory), a PCRAM (phase change random access memory), and a ReRAM (resistive random access memory).

14. A semiconductor storage device comprising:
a first semiconductor storage area which includes a memory cell including a magnetoresistive element;
a second semiconductor storage area which includes a memory cell including a magnetoresistive element;
a reference circuit;
a sense amplifier which senses data stored in the first semiconductor storage area and the second semiconductor storage area; and
a control circuit,
wherein:
a first sense period indicative of a period which is needed for a first sense operation in which the sense amplifier senses data, at a time of receiving a first operation mode selection signal which selects a first operation mode, is longer than a second sense period indicative of a period which is needed for a second sense operation in which the sense amplifier senses data, at a time of receiving a second operation mode selection signal which selects a second operation mode,
the data stored in the first semiconductor storage area or the second semiconductor storage area is sensed in the first operation mode by using the reference circuit, and
the data stored in the first semiconductor storage area is sensed in the second operation mode by using the second semiconductor storage area.

15. The device of claim 14 , wherein:
the first operation mode selection signal includes a first start signal for starting the first sense operation, a first termination signal for terminating the first sense operation, and a first output signal for causing the sense amplifier to output a result of the first sense operation, and
the second operation mode selection signal includes a second start signal, a second terminati

Assignees

• Toshiba Kk
• Toshiba Memory Corp

Inventors

• Katayama Akira

Classifications

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title