Apparatus and method for collaborative adaptation of hierarchically-designed schematics to variant design requirements

Patent metadata

Field	Value
Publication number	US-9760666-B1
Application number	US-201615169239-A
Country	US
Kind code	B1
Filing date	May 31, 2016
Priority date	May 31, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A planned schematic for an electronic system is hierarchically divided into base-level schematic blocks which may be designed individually. In accordance with a plurality of sets of design requirements, variant overlays are designed for each base-level schematic block, each overlay including variant parameter values which may replace corresponding parameter values of the schematic blocks. The schematic blocks are integrated to generate a system-level schematic, and the variant overlays for a given set of design requirements are merged to generate a system variant overlay. Parameter values of the system variant overlay may then replace corresponding parameter values of the system-level schematic to generate a variant schematic for the given set of design requirements. Using this system and methodology, variant designs may be collaboratively generated by multiple designers each with expertise in particular schematic blocks and/or variant requirements, and may be shared either at the system level or at lower levels.

First claim

What is claimed is:

1. A system for adapting a root system-level schematic representation of an electronic system to at least one variant set of design requirements, the root system-level schematic hierarchically defining a plurality of base-level schematic blocks each including at least one component and at least one parameter, the system comprising:
a variant editor executable to generate a plurality of block variant overlays, each block variant overlay associated with one of the variant sets of design requirements and one of the base-level schematic blocks of the root system-level schematic, each block variant overlay defining at least one variant parameter value for the associated base-level schematic block according to the associated variant set of design requirements;
an integrator module executable to:
merge the block variant overlays associated with the same variant set of design requirements to generate a system variant overlay, the system variant overlay including all variant parameter values of the merged block variant overlays, the system variant overlay being associated with the variant set of design requirements, and
assign the variant parameter values of the system variant overlay to the corresponding parameters of the root system-level schematic to generate a variant system-level schematic associated with the variant set of design requirements; and

at least one memory defining at least one system-level variant database storing the system variant overlays.

2. The system of claim 1 , wherein the at least one memory is further configured to store, for each base-level schematic block, a combined block variant database containing the block variant overlays associated with the base-level schematic block.

3. The system of claim 1 , wherein the at least one memory is further configured to store, for at least one base-level schematic block, a plurality of distributed block variant databases each assigned to one of the variant sets of design requirements, each distributed block variant database containing at least one block variant overlay associated with the base-level schematic block and the assigned variant set of design requirements.

4. The system of claim 1 , wherein the at least one system-level variant database includes a plurality of distributed system-level variant databases each assigned to one of the variant sets of design requirements, each distributed system-level variant database containing at least one system variant overlay associated with the assigned variant set of design requirements.

5. The system of claim 1 , wherein:
the root system-level schematic is hierarchically divided into at least one intermediate level of a plurality of intermediate-level schematic blocks, at least one intermediate-level schematic block hierarchically divided into a plurality of base-level schematic blocks; and
the integrator module is further executable to:
merge block variant overlays sharing an association with a variant set of design requirements and associated with a base-level schematic block of a shared intermediate-level schematic block to generate an intermediate variant overlay, the intermediate variant overlay including all variant parameter values of the merged block variant overlays, the intermediate variant overlay associated with the variant set of design requirements and the shared intermediate-level schematic block, and
merge intermediate variant overlays sharing an association with a variant set of design requirements to generate a system variant overlay, the system variant overlay including all variant parameter values of the merged intermediate-level variant overlays, the system variant overlay associated with the variant set of design requirements.

6. The system of claim 5 , wherein the integrator module is further executable to assign parameter values of an intermediate variant overlay to the corresponding parameters of an associated intermediate-level schematic block to generate a variant intermediate-level schematic block associated with the variant set of design requirements.

7. The system of claim 5 , wherein the at least one memory is further configured to store, for each intermediate-level schematic block, a combined intermediate variant database containing the intermediate variant overlays associated with the intermediate-level schematic block.

8. The system of claim 5 , wherein the at least one memory is further configured to store, for at least one intermediate-level schematic block, a plurality of distributed intermediate variant databases each assigned to one of the variant sets of design requirements, each distributed intermediate variant database containing at least one intermediate variant overlay associated with the intermediate-level schematic block and the assigned variant set of design requirements.

9. A system for generating a plurality of system-level schematics representation of electronic systems, the system-level schematics sharing a hierarchy defining a plurality of base-level schematic blocks, each system-level schematic adapted to one of a plurality of variant sets of design requirements, the system comprising:
a schematic editor executable to generate a plurality of base-level schematic block shared by the plurality of system-level schematics, each base-level schematic block including at least one component and at least one parameter;
a variant editor executable to generate a plurality of block variant overlays, each block variant overlay associated with one of the variant sets of design requirements and one of the base-level schematic blocks of the system-level schematics, each block variant overlay defining at least one variant parameter value for the associated base-level schematic block according to the associated variant set;
an integrator module executable to:
integrate the base-level schematic blocks to generate a root system-level schematic including the components of each of the base-level schematic blocks,
merge the block variant overlays associated with the same variant set of design requirements to generate a system variant overlay, the system variant overlay including all variant parameter values of the merged block variant overlays, the system variant overlay being associated with the variant set of design requirements, and
assign the parameter values of the system variant overlay to the corresponding parameters of the root system-level schematic to generate a variant system-level schematic associated with the variant set of design requirements; and

at least one memory defining at least one system-level variant database storing the system variant overlays.

10. The system of claim 9 , wherein:
the hierarchy of the system-level schematics includes at least one intermediate level of a plurality of intermediate-level schematic blocks, at least one intermediate-level schematic block hierarchically divided into a plurality of base-level schematic blocks; and
the integrator module is further executable to:
merge block variant overlays sharing an association with a variant set of design requirements and associated with a base-level schematic block of a shared intermediate-level schematic block to generate an intermediate variant overlay, the intermediate variant overlay including all variant parameter values of the merged block variant overlays, the intermediate variant overlay associated with the variant set of design requirements and the shared intermediate-level schematic block, and
merge intermediate variant overlays sharing an association with a variant set of design requirements to generate a system variant overlay, the system variant overlay including all variant parameter values of the merged intermediate-level variant overlays, the system var

Assignees

• Cadence Design Systems Inc

Inventors

• Gandotra Shilpa
• Chandra Aditya
• Goel Gunjan
• Singh Inderpal
• Gupta Nikhil
• Jain Ishani

Classifications

• G06F2111/12

  Symbolic schematics · CPC title

• G06F30/30 Primary

  Circuit design · CPC title

• G06F17/5045 Primary

  Physics · mapped topic

• G06F2217/74

  Physics · mapped topic

• H05K3/0005

  for designing circuits by computer · CPC title