Floating-gate transistor array for performing weighted sum computation

Patent metadata

Field	Value
Publication number	US-9760533-B2
Application number	US-201414459577-A
Country	US
Kind code	B2
Filing date	Aug 14, 2014
Priority date	Aug 14, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.

First claim

What is claimed is:

1. A weighted sum system, comprising:
an array of current source modules interconnected and arranged into rows and columns, where each current source module includes a field effect transistor and a charge receptacle electrically isolated but capacitively coupled to a channel region of the transistor, wherein, for each row of current source modules, one of a source terminal or a drain terminal for each current source module in the row of current source modules is electrically connected together at a select node and the other of the source terminal and the drain terminal for each current source module in the row of current source modules is electrically connected to one of a plurality of output nodes, such that current flowing through a given current source module is unaffected by operation of remainder of the current source modules in the array of current source modules;
a control circuit electrically connected to each current source module and operates to selectively activate a given column of current source modules in the array of current source modules;
an input circuit electrically connected to select node for each row of current source modules and operates to form a non-zero voltage across each current source module in a selected row of current source modules;
a set of input transistors interposed between the input circuit and the array of current source modules, for each input transistor, a gate terminal is electrically coupled to the input circuit, one of a source terminal or a drain terminal for each input transistor in the set of input transistors is electrically coupled together and the other of the source terminal and the drain terminal for each input transistor in the set of input transistors is electrically connected to one of select nodes in the array of current source modules; and
an output circuit electrically connected to the plurality of output nodes via a common output node, the output circuit operates, substantially independently from amount of current that is being sourced, to maintain voltage at the common output node at a reference voltage and generates an output which is correlated to current that is being sourced collectively by the array of current source modules.

2. The weighted sum system of claim 1 wherein the input circuit selectively activates a given row of current source modules by forming a non-zero voltage across each current source module in the given row of current source modules.

3. The weighted sum system of claim 1 further comprises
a second array of current source modules interconnected and arranged into rows and columns, where each current source module in the second array of current source modules includes a field effect transistor and a charge receptacle electrically isolated but capacitively coupled to a channel region of the transistor, wherein, for each row of current source modules, one of a source terminal or a drain terminal for each current source module in the row of current source modules is electrically connected together at a secondary select node and the other of the source terminal and the drain terminal for each current source module in the row of current source modules is electrically connected to one of the plurality of output nodes, such that the current flowing through a given current source module in the second array of current source modules is unaffected by operation of remainder of the current source modules in the second array of current source modules; and
a second input circuit electrically connected to an input node for each row of current source modules in the second array of current source modules and operates to selectively activate a given row of current source modules in the second array of current source modules, where the control circuit selectively applies a voltage to the control nodes in the array of current source modules that causes current to flow through the current source modules away from the control node and the control circuit applies a voltage to the control nodes in the second array of current source modules that causes current to flow through the current source modules towards from the control node.

4. The weighted sum system of claim 1 wherein, for each row of current source modules, the other of a source terminal or a drain terminal for each current source module in the row of current source modules is electrically connected together at one output node in the plurality of output nodes.

5. The weighted sum system of claim 1 wherein, for each column of current source modules, the other of a source terminal or a drain terminal for each current source module in the column of current source modules is electrically connected together at one output node in the plurality of output nodes.

6. The weighted sum system of claim 1 wherein the output circuit is further defined as at least one of an operational amplifier or an operational transconductance amplifier.

7. The weighted sum system of claim 1 further comprises a multiplexer having a plurality of inputs and an output, such that inputs of the multiplexer are selectively coupled to the output nodes of each row of current source modules and the output of the multiplexer is electrically connected to the common output node.

8. A weighted sum system, comprising:
an array of current source modules interconnected and arranged into rows and columns, where each current source module includes a field effect transistor and a charge receptacle electrically isolated but capacitively coupled to a channel region of the transistor, wherein, for each row of current source modules, one of a source terminal or a drain terminal for each transistor in the row of current source modules is electrically connected together at a select node and the other of the source terminal and the drain terminal for each transistor in the row of current source modules is electrically connected to one of a plurality of output nodes, such that current flowing through a given current source module is unaffected by operation of remainder of the current source modules in the array of current source modules;
a control circuit electrically connected to each current source module and operates to selectively activate a given column of current source modules in the array of current source modules;
a set of input transistors electrically connected to select nodes in the array of current source modules, each input transistor in the set of input transistors has one of a source terminal or a drain terminal electrically coupled to one of select nodes in the array of current source modules;
an input circuit electrically connected to a gate terminal of each input transistor and operates to form a non-zero voltage across each current source module in a selected row of current source modules; and
an output circuit electrically connected to the plurality of output nodes via a common output node, the output circuit operates to maintain voltage constant at the common output node and generates an output which is correlated to current that is being sourced collectively by the array of current source modules.

9. The weighted sum system of claim 8 wherein the input circuit selectively activates a given row of current source modules by forming a non-zero voltage across each current source module in the given row of current source modules.

10. The weighted sum system of claim 8 further comprises
a second array of current source modules interconnected and arranged into rows and columns, where each current source module in the second array of current source modules includes a field effect transistor and a charge receptacle electrically isolated but capacitively coupled to a channel region of the transistor, wherein, for each row

Assignees

• Univ Michigan Regents
• Isocline Eng Llc
• The Regents On The Univ Of Michigan

Inventors

• Fick Laura
• Blaauw David T
• Sylvester Dennis
• Henry Michael B
• Fick David Alan

Classifications

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G06N3/06

  Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons · CPC title

• G06F17/11 Primary

  for solving equations {, e.g. nonlinear equations, general mathematical optimization problems (optimization specially adapted for a specific administrative, business or logistic context G06Q10/04)} · CPC title

• G06N3/063 Primary

  using electronic means · CPC title