Disaggregated server architecture for data centers

Patent metadata

Field	Value
Publication number	US-9760527-B2
Application number	US-201514931264-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	Mar 13, 2013
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A system comprising a unified interconnect network, a plurality of process memory modules, and a plurality of processor modules configured to share access to the memory modules via the unified interconnect network. Data may be communicated between a plurality of processor modules and a plurality of shared resource pools via a unified interconnect network, wherein the communications comprise a protocol that is common to all resource pools, and wherein each resource pool comprises a plurality of resource modules each configured to perform a common function. Further, a network interface controller (NIC) module may be configured to receive data from a plurality of processor modules via a unified interconnect network, and provide core network connectivity to the processor modules.

First claim

What is claimed is:

1. A system comprising:
a unified interconnect network;
a memory pool comprising a plurality of first network elements coupled to the unified interconnect network and each comprising a process memory module; and
a processor pool comprising a plurality of second network elements coupled to the unified interconnect network and each comprising a processor module;
wherein each of the first network elements is physically separate from each of the second network elements,
wherein each of the second network elements is configured to share access to the process memory modules in the memory pool via the unified interconnect network, and
wherein the unified interconnect network employs a protocol common to the process memory modules and the processor modules in the memory pool and the processor pool.

2. The system of claim 1 , wherein the unified interconnect network comprises a Peripheral Component Interconnect Express (PCI-e) network.

3. The system of claim 1 , wherein the unified interconnect network comprises an Infiniband network.

4. The system of claim 1 further comprising a plurality of third network elements coupled to the unified interconnect network and each comprising a data storage module configured for data storage, wherein the processor modules are further configured to share access to the data storage modules via the unified interconnect network.

5. The system of claim 4 further comprising a plurality of fourth network elements coupled to the unified interconnect network and each comprising a network interface controller module configured for core network connectivity, wherein the processor modules are further configured to share access to the network interface controller modules via the unified interconnect network.

6. The system of claim 5 further comprising a plurality of fifth network elements coupled to the unified interconnect network and each comprising a process acceleration module, wherein the processor modules are further configured to share access to the process acceleration modules via the unified interconnect network.

7. The system of claim 6 , wherein the process acceleration modules comprise a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or combinations thereof.

8. The system of claim 6 , wherein each processor module is positioned in a separate network element from each storage module, network interface controller module, and process acceleration module.

9. The system of claim 1 , wherein the processor modules do not comprise local process memory or local data storage.

10. The system of claim 1 , wherein each processor module is positioned in one of a plurality of processor servers, and wherein each process memory module is positioned in one of a plurality of memory servers that are each separate from the processor servers.

11. A method comprising:
communicating data between a plurality of processor modules and a plurality of shared resource pools via a unified interconnect network,
wherein each processor module is positioned in a physically separate processor server,
wherein each shared resource pool comprises at least one resource module,
wherein each resource module is positioned in a physically separate resource specific server, and
wherein all resource modules in each shared resource pool are configured to perform a common function.

12. The method of claim 11 further comprising upgrading one of the processor modules while communicating data via the unified interconnect network without upgrading resource modules, wherein the one processor module is upgraded by replacing one of the processor servers.

13. The method of claim 11 , wherein at least one of the shared resource pools comprises a process memory module pool, and wherein the method further comprises sharing storage resources of the process memory module pool among the processor modules.

14. The method of claim 11 , wherein at least one of the shared resource pools comprises a process acceleration module pool, and wherein the method further comprises sharing process resources of the process acceleration module pool among the processor modules.

15. The method of claim 11 , wherein at least one of the shared resource pools comprises a data storage module pool, and wherein the method further comprises sharing storage resources of the data storage module pool among the processor modules.

16. The method of claim 11 , wherein at least one of the shared resource pools comprises a network interface controller module pool, and wherein the method further comprises sharing connectivity resources of the network interface controller module pool among the processor modules.

17. An apparatus comprising:
a resource module having a processor; and
at least one storage device coupled to the resource module and configured to store instructions executable by the processor such that when executed, the instructions cause the resource module to:
receive data from a plurality of processor modules via a unified interconnect network, wherein each processor module is positioned in a physically separate processor server, and wherein the resource module is positioned in a server that is physically separate from each processor server; and
provide shared resources to the processor modules via the unified interconnect network.

18. The apparatus of claim 17 , wherein the resource module comprises a network interconnect (NIC) module, and wherein the shared resources comprise connectivity resources that are configured to communicate processor module data to a core network.

19. The apparatus of claim 17 , wherein the resource module comprises a process acceleration module, and wherein the shared resources comprise processing resources that are configured to process processor module requests.

20. The apparatus of claim 17 , wherein the resource module comprises a process memory module, and wherein the shared resources comprise storage resources that are configured to store processor data related to active processes of the processor modules.

Assignees

• Futurewei Technologies Inc

Inventors

• Egi Norbert
• Shi Guangyu

Classifications

• G06F15/17331 Primary

  Distributed shared memory [DSM], e.g. remote direct memory access [RDMA] · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F15/786

  using a single memory module · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title