Hybrid tracking of transaction read and write sets

Patent metadata

Field	Value
Publication number	US-9760494-B2
Application number	US-201514748381-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Jun 24, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mispredictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.

First claim

We claim:

1. A computer program product for tracking of processor transactional read and write sets, the computer program product comprising a computer readable storage device having program code embodied therewith, the program code executable by a processing unit to:
maintain a non-speculative read set indication of non-speculative reads of data stored in a cache by a processor cache unit for a transaction by a first requestor;
maintain a non-speculative write set indication of non-speculative writes of written data stored in the cache by the processor cache unit by the first requestor;
maintain a queue of addresses corresponding to speculatively executed memory read instructions corresponding to speculative members of a read set;
maintain a queue of addresses corresponding to speculatively executed memory write instructions corresponding to speculative members of a write set;
perform a transaction interference resolution responsive to receiving a request for data by a remote processor, including determining a potential transaction interference exclusively conflicting with a speculative instruction; and
hold a response to the received request until the speculative instruction is in a state selected from the group of: committed and flushed.

2. The computer program product of claim 1 , further comprising program code executable by the processing unit to:
responsive to determining an instruction is next to complete, remove an entry corresponding to the instruction from a pending queue representing speculative accesses; and
update one of the non-speculative read set indication and the non-speculative write set indication.

3. The computer program product of claim 2 , wherein the update of the non-speculative read and write set are deferred until execution of the instructions is committed.

4. The computer program product of claim 1 , wherein the received request is a write request, further comprising the transaction interference additionally checking the memory read pending address queue and the non-speculative read set for interference with the requested address.

5. The computer program product of claim 1 , wherein the memory read queue and the memory write queue maintain an order of the addresses.

6. The computer program product of claim 5 , wherein the addresses being added to the queue are responsive to the speculative execution of a memory read or write instruction.

7. The computer program product of claim 1 , further comprising responsive to a flushing of an instruction corresponding to at least one entry in one of a read and write pending address queue, program code to remove the at least one corresponding entry from one of a read and write pending address queue.

8. The computer program product of claim 7 , further comprising program code to flush all instructions subsequent to the flushing of the instruction, and remove any queue entries corresponding to the subsequent instructions.

9. A computer system comprising:
a processing unit operatively coupled to memory;
a tool in communication with the processing unit to track processor transactional read and write sets, including:
maintain a non-speculative read set indication of non-speculative reads of data stored in a cache by a processor cache unit for a transaction by a first requestor;
maintain a non-speculative write set indication of non-speculative writes of written data stored in the cache by the processor cache unit by the first requestor;
maintain queue of addresses corresponding to speculatively executed load instructions corresponding to speculative members of a read set;
maintain a queue of addresses corresponding to speculatively executed store instructions corresponding to speculative members of a write set;
perform a transaction interference resolution responsive to receiving a request for data by a remote processor, including determining a potential transaction interference exclusively conflicting with a speculative instruction; and
hold a response to the received request until the speculative instruction is in a state selected from the group of: committed and flushed.

Assignees

• IBM

Inventors

• Gschwind Michael Karl
• Salapura Valentina
• Shum Chung-Lung K

Classifications

• A45D40/00

  Casings or accessories specially adapted for storing or handling solid or pasty toiletry or cosmetic substances, e.g. shaving soaps or lipsticks (features common to containers for handling powdery or liquid toiletry or cosmetic substances A45D33/00-A45D37/00; cosmetic or like preparations A61K8/00, A61Q; sample tables or the like G09F5/00) · CPC title

• B29L2031/7184

  Lipstick holders · CPC title

• G06F9/528

  by using speculative mechanisms · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title