Pixel driving circuit and driving method thereof, array substrate and display apparatus

US9760199B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9760199-B2
Application numberUS-201414443445-A
CountryUS
Kind codeB2
Filing dateSep 2, 2014
Priority dateMay 14, 2014
Publication dateSep 12, 2017
Grant dateSep 12, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A pixel driving circuit and method, an array substrate and a display apparatus are provided. The driving circuit includes: a data line, a first scan line, a second scan line, a power supply line, a light emitting device, a display sub-circuit and a photosensitive sub-circuit; the display sub-circuit is connected to the data line, the first scan line, the second scan line, the power supply line and the light emitting device, and is configured to drive the light emitting device to emit light for display under the control of the first scan line, the second scan line, the data line and the power supply line; and the photosensitive sub-circuit is connected to the second scan line, and is configured to sense a touch action under the control of the second scan line.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel driving circuit comprising: a data line, a first scan line, a second scan line, a power supply line, a light emitting device, a display sub-circuit and a photosensitive sub-circuit; wherein the display sub-circuit is directly connected to the data line, the first scan line, the second scan line, the power supply line and the light emitting device, and is configured to drive the light emitting device to emit light for display under control of the first scan line, the second scan line, the data line and the power supply line; and the photosensitive sub-circuit is directly connected to the second scan line, and is configured to sense a touch action under control of the second scan line; wherein the photosensitive sub-circuit comprises: a reference signal line, a signal detecting line, a first storage capacitor, a signal sensing unit and a signal reading-writing unit; wherein the signal reading-writing unit is directly connected to a first terminal of the first storage capacitor, the second scan line and the signal detecting line, and is configured to write a signal on the signal detecting line into the first terminal of the first storage capacitor, or to read out a signal stored in the first storage capacitor and transmit the same to the signal detecting line under the control of the second scan line; and the signal sensing unit is directly connected to the second scan line, the reference signal line and the first storage capacitor, and is configured to write a signal on the reference signal line and a sensed photosensitive signal into the first storage capacitor under the control of the second scan line; the signal reading-writing unit comprises a sixth transistor having a gate connected to the second scan line, a source connected to the first terminal of the first storage capacitor, and a drain connected to the signal detecting line, and being configured to write the signal on the signal detecting line into the first terminal of the first storage capacitor, or to read out the signal stored in the first storage capacitor and transmit the same to the signal detecting line under the control of the second scan line; and the signal sensing unit comprises a seventh transistor and a photosensitive transistor, wherein the seventh transistor has a gate directly connected to the second scan line, a source directly connected to the reference signal line and a drain directly connected to a gate of the photosensitive transistor and a second terminal of the first storage capacitor, and is configured to write the signal on the reference signal line into the second terminal of the first storage capacitor under the control of the second scan line; and the photosensitive transistor has a gate connected to a source thereof and a drain connected to the first terminal of the first storage capacitor, and is configured to sense the photosensitive signal and write the same into the first terminal of the first storage capacitor. 2. The pixel driving circuit of claim 1 , wherein the display sub-circuit comprises a second storage capacitor, a driving transistor, a charging and discharging unit, and a light emitting control unit; wherein the driving transistor has a source connected to a first terminal of the second storage capacitor, and a drain connected to a light emitting device; the charging and discharging unit is connected to the data line, the first scan line, the second scan line, the power supply line, the second storage capacitor and the driving transistor, and is configured to charge the two terminals of the second storage capacitor and a gate of the driving transistor such that a voltage across the two terminals of the second storage capacitor is a voltage on the power supply line and a voltage at the gate of the driving transistor is a voltage on the data line under the control of the first and second scan lines, and to further discharge the second storage capacitor such that a voltage difference between the gate and the source of the driving transistor is a threshold voltage of the driving transistor under the control of the first and second scan lines; and the light emitting control unit is connected to the first scan line, a second terminal of the second storage capacitor and the driving transistor, and is configured to make the driving transistor drive the light emitting device to emit light under the control of the first scan line. 3. The pixel driving circuit of claim 2 , wherein the charging and discharging unit comprises: a first transistor, a second transistor, a fourth transistor and a fifth transistor; wherein the first transistor has a gate connected to the second scan line, a source connected to the power supply line, and a drain connected to the first terminal of the second storage capacitor, and is configured to, under the control of the second scan line, write the voltage on the power supply line into the first terminal of the second storage capacitor, and to further disconnect the first terminal of the second storage capacitor and the power supply line, so as to discharge the voltage across the two terminals of the second storage capacitor to the voltage difference between the gate and the source of the driving transistor which is the threshold voltage of the driving transistor; the second transistor has a gate connected to the first scan line, a source connected to the second terminal of the second storage capacitor, and a drain connected to ground, and is configured to connect the second terminal of the second storage capacitor to ground under the control of the first scan line; the fourth transistor has a gate connected to the first scan line, a source connected to the data line, and a drain connected to the gate of the driving transistor, and is configured to set the voltage at the gate of the driving transistor to the voltage on the data line under the control of the first scan line; and the fifth transistor has a gate connected to the first scan line, a source connected to the light emitting device, and a drain connected to ground, and is configured to shorten the light emitting device to connect the light emitting device to ground under the control of the first scan line. 4. The pixel driving circuit of claim 3 , wherein the light emitting control unit comprises a third transistor, wherein the third transistor has a gate connected to the first scan line, a source connected to the second terminal of the second storage capacitor, and a drain connected to the gate of the driving transistor, and is configured to form a path between the second terminal of the second storage capacitor and the gate of the driving transistor. 5. The pixel driving circuit of claim 4 , wherein the light emitting device is an organic light emitting diode having an anode connected to the drain of the driving transistor and to the source of the fifth transistor and a cathode connected to ground. 6. A method for driving a pixel driving circuit, wherein the pixel driving circuit comprises: a data line, a first scan line, a second scan line, a power supply line, a light emitting device, a display sub-circuit and a photosensitive sub-circuit; the photosensitive sub-circuit comprises: a reference signal line, a signal detecting line, a first storage capacitor, a signal sensing unit and a signal reading-writing unit; the method comprising: driving the light emitting device to emit light for display by the display sub-circuit under the control of the first scan line, the second scan line, the data line and the power supply line; and sensing a touch action by the photosensitive sub-circuit under the control of the second scan line; wherein sensing the touch action by the photosensitive sub-circuit under the control of the second scan line comprises: applying a second scan valid signal to the s

Assignees

Inventors

Classifications

  • G06F3/0412Primary

    Digitisers structurally integrated in a display · CPC title

  • Details of drivers for scan electrodes · CPC title

  • by opto-electronic means · CPC title

  • Control or interface arrangements specially adapted for digitisers · CPC title

  • Precharge or discharge of column electrodes before or after applying exact column voltages · CPC title

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What does patent US9760199B2 cover?
A pixel driving circuit and method, an array substrate and a display apparatus are provided. The driving circuit includes: a data line, a first scan line, a second scan line, a power supply line, a light emitting device, a display sub-circuit and a photosensitive sub-circuit; the display sub-circuit is connected to the data line, the first scan line, the second scan line, the power supply line …
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Beijing Boe Optoelectronics Tech Co Ltd, Boe Tech Group Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0412. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).