Information processing apparatus

US9760127B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9760127-B2
Application numberUS-201514667751-A
CountryUS
Kind codeB2
Filing dateMar 25, 2015
Priority dateMar 28, 2014
Publication dateSep 12, 2017
Grant dateSep 12, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A settlement processing apparatus as an information processing apparatus includes a first substrate, a second substrate which is provided so as to face the first substrate, a frame member which supports the first substrate and the second substrate on the inner surface side of a wall surface portion surrounding the external forms of the first substrate and the second substrate, and a tamper detection circuit which is disposed within a secure region surrounded by the first substrate, the second substrate, and the frame member and detects the release of blocking of the secure region. An information processing apparatus which is small, secures the degree of freedom in design, and has high tamper resistance is provided.

First claim

Opening claim text (preview).

What is claimed is: 1. An information processing apparatus, comprising: a first substrate; a second substrate which faces the first substrate; a frame member which includes a wall surface portion surrounding a secure region together with the first substrate and the second substrate; a tamper detection circuit which is disposed within the secure region and detects release of blocking of the secure region; and a substrate connection circuit which electrically connects a first surface that is a first side of the secure region of the first substrate and a second surface that is a second side of the secure region of the second substrate, when the frame member contacts the first substrate and the second substrate, a length of a portion of the substrate connection circuit which crosses the secure region is greater than a distance between the first substrate and the second substrate, and in a plan view perpendicular to the first substrate and the second substrate, peripheries of the first substrate and the second substrate are each smaller than and within a periphery of the frame member. 2. The information processing apparatus of claim 1 , further comprising: a first tamper detection pattern which is in the first substrate and is electrically connected to the tamper detection circuit; a second tamper detection pattern which is in the second substrate and is electrically connected to the tamper detection circuit; two electrodes which open an electric circuit of the first tamper detection pattern or the second tamper detection pattern; and an electrode connection member which is independent of the first substrate and the second substrate and electrically connects the two electrodes. 3. The information processing apparatus of claim 2 , wherein the electrode connection member is disposed between the first substrate and the second substrate. 4. The information processing apparatus of claim 3 , wherein the electrode connection member includes an elastic member disposed between the first substrate and the second substrate, a conductive film being formed on a surface of the elastic member, and the elastic member is fixed between the first substrate and the second substrate by an elastic force of the elastic member, the conductive film being pressed by the two electrodes to thereby secure electrical connection between the two electrodes. 5. The information processing apparatus of claim 2 , wherein a flexible substrate including a wiring pattern electrically connected to the tamper detection circuit covers at least the entire outer circumference of the wall surface portion. 6. The information processing apparatus of claim 5 , wherein the wiring pattern of the flexible substrate is electrically connected to the tamper detection circuit independently of the first tamper detection pattern and the second tamper detection pattern. 7. The information processing apparatus of claim 1 , wherein the substrate connection circuit is constituted by a flexible foldable substrate having a folded portion. 8. The information processing apparatus of claim 1 , further comprising: an electronic component mounted on one of the first surface of the first substrate and the second surface of the second substrate which is a target to be protected and stores information to be protected. 9. The information processing apparatus of claim 1 , further comprising: a first connector which is disposed on the first side of the secure region of the first substrate and which is connected to one end of the substrate connection circuit; and a second connector which is disposed on the second side of the secure region of the second substrate and which is connected to another end of the substrate connection circuit opposite to the one end of the substrate connection circuit. 10. The information processing apparatus of claim 1 , wherein the substrate connection circuit is a flexible circuit. 11. The information processing apparatus of claim 1 , wherein the tamper detection circuit detects the release of the blocking of the secure region through separation of one of the first substrate and the second substrate from the frame member. 12. The information processing apparatus of claim 11 , wherein the frame member has a shape that is closed in a circumferential direction by the wall surface portion. 13. The information processing apparatus of claim 12 , wherein the frame member includes at least one member mounting portion, the member mounting portion being integral with the frame member and defining an opening, the opening being open to the first surface that is the first side of the secure region of the first substrate and the second surface that is the second side of the secure region of the second substrate. 14. The information processing apparatus of claim 13 , wherein the member mounting portion has a shape that is closed in the circumferential direction. 15. The information processing apparatus of claim 14 , further comprising: a conductive member mounted in the member mounting portion, the tamper detection circuit detecting the separation of one of the first substrate and the second substrate from the frame member via the conductive member. 16. The information processing apparatus of claim 1 , wherein the substrate connection circuit is a flexible foldable substrate having a plurality of folds. 17. The information processing apparatus of claim 16 , wherein the substrate connection circuit is connected to the first surface that is the first side of the secure region of the first substrate via a first connector disposed on the first substrate, the substrate connection circuit is connected to the second surface that is the second side of the secure region of the second substrate via a second connector disposed on the second substrate, and the first connector and the second connector are aligned in a direction perpendicular to the first substrate and the second substrate. 18. The information processing apparatus of claim 17 , wherein the plurality of folds of the flexible foldable substrate are between the first connector and the second connector in the direction perpendicular to the first substrate and the second substrate. 19. The information processing apparatus of claim 1 , further comprising: a flexible substrate including a wiring pattern electrically connected to the tamper detection circuit and covering the wall surface portion of the frame member, wherein the flexible substrate is further between portions of the first substrate and the frame member which abut and between portions of the second substrate and the frame member which abut. 20. The information processing apparatus of claim 1 , wherein, when the frame member contacts the first substrate and the second substrate, a length of each of the conductive members is greater than or equal to the distance between the first substrate and the second substrate.

Assignees

Inventors

Classifications

  • G06F21/86Primary

    Secure or tamper-resistant housings · CPC title

  • G06F1/1656Primary

    Details related to functional adaptations of the enclosure, e.g. to provide protection against EMI, shock, water, or to host detachable peripherals like a mouse or removable expansions units like PCMCIA cards, or to provide access to internal components for maintenance or to removable storage supports like CDs or DVDs, or to mechanically mount accessories (mounting of accessories to a computer display G06F1/1607; display hoods G06F1/1603; cooling arrangements for portable computers G06F1/203) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9760127B2 cover?
A settlement processing apparatus as an information processing apparatus includes a first substrate, a second substrate which is provided so as to face the first substrate, a frame member which supports the first substrate and the second substrate on the inner surface side of a wall surface portion surrounding the external forms of the first substrate and the second substrate, and a tamper dete…
Who is the assignee on this patent?
Panasonic Ip Man Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F21/86. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).