Integrated circuit having regulator controlled based on operational speed

Patent metadata

Field	Value
Publication number	US-9760103-B2
Application number	US-201615157049-A
Country	US
Kind code	B2
Filing date	May 17, 2016
Priority date	May 18, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Aspects of the disclosure include an integrated circuit that includes a first circuit, a first performance detector, and a first regulator. The first circuit is configured to receive a first regulated voltage from a first voltage supply line disposed on the integrated circuit. The first performance detector includes a first speed monitor disposed adjacent to the first circuit, and the first performance detector is configured to generate a first control signal based on a first speed detection result from the first speed monitor. The first speed detection result corresponds to measuring an operational speed of the first circuit. The first regulator is configured to receive a global supply voltage from a power rail and output the first regulated voltage based on the global supply voltage and the first control signal.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first circuit disposed in a first power domain of the integrated circuit and configured to receive a first regulated voltage, the first regulated voltage being received from a first voltage supply line disposed on the integrated circuit and powering the first power domain independently of another power domain of the integrated circuit;
a first performance detector disposed in the first power domain and including a first speed monitor disposed adjacent to the first circuit, the first performance detector being configured to generate a first control signal based on a first speed detection result from the first speed monitor, the first speed detection result corresponding to measuring an operational speed of the first circuit; and
a first regulator configured to
receive a global supply voltage from a power rail, and
output the first regulated voltage to the first circuit based on the global supply voltage and the first control signal regardless of a detected performance of other circuits on the integrated circuit that are disposed outside the first power domain.

2. The integrated circuit of claim 1 , further comprising:
a second circuit disposed in a second power domain of the integrated circuit and configured to receive a second regulated voltage that powers the second power domain from a second voltage supply line disposed on the integrated circuit, the second power domain being different from the first power domain;
a second performance detector disposed in the second power domain and including a second speed monitor disposed adjacent to the second circuit, the second performance detector being configured to generate a second control signal based on a second speed detection result from the second speed monitor, the second speed detection result corresponding to measuring an operational speed of the second circuit; and
a second regulator configured to
receive the global supply voltage from the power rail, and
output the second regulated voltage to the second circuit based on the global supply voltage and the second control signal regardless of a detected performance of other circuits on the integrated circuit that are disposed outside the second power domain.

3. The integrated circuit of claim 1 , wherein
the first performance detector includes a plurality of speed monitors respectively disposed at different locations, the speed monitors being configured to generate speed detection results indicating whether measured operation speeds are greater than a benchmark, respectively; and
the first performance detector further comprises a detection controller configured to generate the first control signal based on the speed detection results from the plurality of speed monitors.

4. The integrated circuit of claim 3 , wherein the detection controller is configured to generate the first control signal by performing a logical combination of the speed detection results received from the plurality of speed monitors.

5. The integrated circuit of claim 1 , wherein the first regulator comprises:
a transistor having a first terminal configured to receive the global supply voltage, a second terminal electrically coupled with the first voltage supply line and configured to output the first regulated voltage, and a control terminal configured to receive a control voltage; and
a control voltage driver configured to output the control voltage based on the first control signal.

6. The integrated circuit of claim 5 , wherein the control voltage driver comprises:
a driving stage having an input node and an output node, the input node of the driving stage being configured to receive the first control signal; and
a low-pass filter electrically coupled between the output node of the driving stage and the control terminal of the transistor.

7. The integrated circuit of claim 6 , wherein the low-pass filter comprises:
a first switch between the output node of the driving stage and an intermediate node;
a second switch between the intermediate node and the control terminal of the transistor, the first switch and the second switch being configured to be turned on alternatively; and
a capacitive device electrically coupled with the intermediate node.

8. The integrated circuit of claim 5 , further comprising:
a pull-up switch configured to selectively couple the control terminal of the transistor to the global supply voltage; and
a pull-down switch configured to selectively couple the control terminal of the transistor to a ground reference voltage.

9. The integrated circuit of claim 5 , wherein
the transistor includes one or more power switch transistors respectively occupying a first area in the integrated circuit and corresponding to a first on/off speed, and
the first circuit includes a plurality of logic transistors respectively occupying a second area in the integrated circuit that is less than any of the first area(s) and that corresponds to a second on/off speed greater than any of the first on/off speed(s).

10. The integrated circuit of claim 1 , wherein the first speed monitor of the first performance detector comprises:
a ring oscillator configured to generate a local clock signal;
a counter configured to generate a done signal indicating whether a number of clock cycles of the local clock signal reaches a threshold after the counter is initialized; and
a monitor controller configured to
receive a reference clock signal and the done signal,
initialize the counter, and
generate a speed detection result based on the done signal and the reference clock signal.

11. The integrated circuit of claim 10 , wherein the monitor controller is further configured to
set a frequency of the local clock signal by configuring a number of inverting devices in a sequential loop of the ring oscillator.

12. A method of adjusting one or more regulated voltages supplied to one or more respective circuits in an integrated circuit, the method comprising:
determining a first speed detection result by a first speed monitor disposed adjacent to a first circuit, the first speed monitor and the first circuit being disposed in a first power domain of in the integrated circuit, the first speed detection result corresponding to measuring an operational speed of the first circuit;
determining a first control signal based on the first speed detection result from the first speed monitor;
receiving, by a first regulator, a global supply voltage from a power rail; and
outputting, by the first regulator based on the global supply voltage and the first control signal regardless of a detected performance of other circuits outside the first power domain, a first regulated voltage that powers the first power domain independently of another power domain of the integrated circuit.

13. The method of claim 12 , further comprising:
determining a second speed detection result by a second speed monitor disposed adjacent to a second circuit, the second speed monitor and the second circuit being disposed in a second power domain of the integrated circuit, the second power domain being different from the first power domain, the second speed detection result corresponding to measuring an operational speed of the second circuit;
determining a second control signal based on the second speed detection result from the second speed monitor;
receiving, by a second regulator, the global supply voltage from the power rail; and
outputting, by the second regulator based on the global supply voltage and the second control signal regardless of a detected performance of other circuits outside the second power domain, a second regula

Assignees

• Marvell Israel (M I S L ) Ltd
• Marvell Israel (M I S L) Ltd

Inventors

• Rosen Eitan

Classifications

• H03K21/38

  Starting, stopping or resetting the counter (counters with a base other than a power of two H03K23/48, H03K23/66) · CPC title

• G05F1/468 Primary

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• G05F1/59

  including plural semiconductor devices as final control devices for a single load · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title