Thin film transistor substrate, liquid crystal display device having the same and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9759968-B2
Application number	US-201414576123-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Feb 12, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A thin film transistor substrate includes a gate electrode on a base substrate, an active pattern on the gate electrode, a source electrode on a first end of the active pattern, a drain electrode on a second end of the active pattern, an organic insulation layer on the source electrode and the drain electrode, and a transparent electrode contacting the drain electrode through a contact opening in the organic insulation layer. The drain electrode is spaced from the source electrode. The organic insulation layer includes a first thickness portion around the contact opening and a second thickness portion adjacent to the first thickness portion. The second thickness portion has a thickness greater than that of the first thickness portion.

First claim

What is claimed is:

1. A thin film transistor substrate comprising:
a gate electrode on a base substrate;
an active pattern on the gate electrode;
a source electrode on a first end of the active pattern;
a drain electrode on a second end of the active pattern, the drain electrode being spaced from the source electrode;
an organic insulation layer on the source electrode and the drain electrode; and
a transparent electrode contacting the drain electrode via a contact opening in the organic insulation layer,
wherein the organic insulation layer comprises a first thickness portion around the contact opening and a second thickness portion surrounding a periphery of the first thickness portion, the second thickness portion having a thickness greater than that of the first thickness portion, an upper surface of the second thickness portion being above an upper surface of the first thickness portion, and
wherein the thickness of the second thickness portion is greater than the thickness of the first thickness portion by about 0.5 μm or more.

2. The thin film transistor substrate of claim 1 , wherein the first thickness portion is over the drain electrode.

3. The thin film transistor substrate of claim 1 , wherein the thickness of the first thickness portion is equal to or less than about 2.0 μm.

4. The thin film transistor substrate of claim 1 , wherein the thickness of the second thickness portion is equal to or greater than about 2.0 μm.

5. The thin film transistor substrate of claim 1 , wherein a width of the contact opening is equal to or greater than about 1.0 μm and equal to or less than about 2.0 μm.

6. The thin film transistor substrate of claim 1 , further comprising an inorganic insulation layer between the drain electrode and the organic insulation layer.

7. The thin film transistor substrate of claim 1 , wherein the transparent electrode is over the first thickness portion of the organic insulation layer.

8. The thin film transistor substrate of claim 1 , wherein a first height of the first thickness portion of the organic insulation layer is less than a second height of the second thickness portion of the organic insulation layer with respect to the base substrate.

9. The thin film transistor substrate of claim 1 , wherein the second thickness portion of the organic insulation layer surrounds a periphery of the first thickness portion of the organic insulation layer.

10. The thin film transistor substrate of claim 1 , wherein an end of the transparent electrode is on the first thickness portion of the organic insulation layer.

11. The thin film transistor substrate of claim 1 , wherein a first upper surface and a second upper surface of the first thickness portion extend from the contact opening in opposite directions, respectively, and a length of the first upper surface is substantially same as a length of the second upper surface.

12. A liquid crystal display panel comprising:
an array substrate comprising a thin film transistor;
an opposing substrate facing the array substrate; and
a liquid crystal layer between the array substrate and the opposing substrate,
wherein the array substrate further comprises:
a gate line on a base substrate, the gate line extending in a first direction and being electrically coupled to the thin film transistor;
a data line extending in a second direction crossing the first direction, the data line being electrically coupled to the thin film transistor;
an organic insulation layer on the thin film transistor; and
a pixel electrode contacting a drain electrode of the thin film transistor at a contact opening in the organic insulation layer,

wherein the organic insulation layer comprises a first thickness portion around the contact opening and a second thickness portion adjacent to the first thickness portion, the second thickness portion having a thickness greater than that of the first thickness portion, an upper surface of the second thickness portion being above an upper surface of the first thickness portion, and
wherein the thickness of the second thickness portion is greater than the thickness of the first thickness portion by about 0.5 μm or more.

13. The liquid crystal display panel of claim 12 , wherein the first thickness portion is over the drain electrode.

14. The liquid crystal display panel of claim 12 , wherein a thickness of the first thickness portion is equal to or less than about 2.0 μm.

15. The liquid crystal display panel of claim 12 , wherein a width of the contact opening is equal to or greater than about 1.0 μm and equal to or less than about 2.0 μm.

16. The liquid crystal display panel of claim 12 , wherein the second thickness portion of the organic insulation layer surrounds a periphery of the first thickness portion of the organic insulation layer.

17. The liquid crystal display panel of claim 12 , wherein an end of the pixel electrode is on the first thickness portion of the organic insulation layer.

18. The liquid crystal display panel of claim 12 , wherein a first upper surface and a second upper surface of the first thickness portion extend from the contact opening in opposite directions, respectively, and a length of the first upper surface is substantially same as a length of the second upper surface.

Assignees

• Samsung Display Co Ltd

Inventors

• Cho Ki-Hyun
• Park Sung-Kyun
• Kim Ji-Hyun
• Park Jeong-Min
• Lee Jung-Soo
• Chun Jun
• Ju Jin-Ho

Classifications

• H01L29/78606

  Electricity · mapped topic

• G02F1/136227 Primary

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F2001/136231

  Physics · mapped topic

• H01L29/7869

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic