Programmable test instrument

Patent metadata

Field	Value
Publication number	US-9759772-B2
Application number	US-201113284483-A
Country	US
Kind code	B2
Filing date	Oct 28, 2011
Priority date	Oct 28, 2011
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

In general, a test instrument includes a first processing system that is programmable to run one or more test programs to test a device interfaced to the test instrument, and that is programmed to control operation of the test instrument, a second processing system that is dedicated to device testing, the second processing system being programmable to run one or more test programs to test the device, and programmable logic configured to act as an interface between the test instrument and the device, the programmable logic being configurable to perform one or more tests on the device. The first processing system and the second processing system are programmable to access the device via the programmable logic.

First claim

What is claimed is:

1. A test instrument comprising:
programmable logic programmed to act as an interface to a device under test, the programmable logic being configurable to perform one or more tests on the device, the programmable logic specifying a number of input ports and a number of output ports on the interface to the device;
a first processing system that is programmable to run one or more test programs to test the device via the interface; and
a second processing system that is dedicated to device testing, the second processing system comprising a plurality of embedded processing devices dedicated to device testing, the embedded processing devices being programmable to run one or more test programs to test the device via the interface;
wherein the second processing system is configured to transmit test results from the programmable logic to the first processing system;
wherein the programmable logic is configurable to execute one or more of the tests separately of the second processing system; and
wherein the first processing system has a first testing latency, the second processing system has a second testing latency, and the programmable logic has a third testing latency, the first testing latency being greater than the second testing latency, and the second testing latency being greater than the third testing latency.

2. The test instrument of claim 1 , wherein the first testing latency is on the order of milliseconds, the second testing latency is on the order of microseconds, and the third testing latency is on the order of nanoseconds.

3. The test instrument of claim 1 , wherein the first processing system is programmed to run one or more test programs to test the device interfaced to the test instrument;
wherein the second processing system is not programmed to run one or more test programs to test the device; and
wherein the programmable logic is not configured to perform one or more tests on the device.

4. The test instrument of claim 1 , wherein the first processing system is not programmed to run one or more test programs to test the device interfaced to the test instrument;
wherein the second processing system is programmed to run one or more test programs to test the device; and
wherein the programmable logic is not configured to perform one or more tests on the device.

5. The test instrument of claim 1 , wherein the first processing system is not programmed to run one or more test programs to test the device interfaced to the test instrument;
wherein the second processing system is not programmed to run one or more test programs to test the device; and
wherein the programmable logic is configured to perform one or more tests on the device.

6. The test instrument of claim 1 , wherein the first processing system comprises a processing device that executes a windowing operating system;
wherein each of the embedded processing devices is for testing a different device to be tested by the test instrument; and
wherein the programmable logic comprises one or more field programmable gate arrays (FPGAs), each of the one or more FPGAs being for testing a different device to be tested by the test instrument.

7. The test instrument of claim 1 , wherein the programmable logic comprises field programmable gate arrays (FPGAs), at least one of the FPGAs being pre-programmed to perform functions that do not involve exchange of data with the device to be tested.

8. The test instrument of claim 1 , wherein at least one of the first processing system, the second processing system, and the programmable logic is reprogrammable via one or more interfaces.

9. The test instrument of claim 1 , wherein the first processing system is programmable to control operation of the test instrument by performing one or more of the following: exchanging communication between the test instrument and one or more entities over a network, scanning the test instrument for malware, and performing memory management functions.

10. The test instrument of claim 1 , wherein at least two of the programmable logic, the first processing system, and the second processing system are configured to perform testing operations on the device concurrently.

11. A test instrument comprising:
a first tier system for interacting with an environment external to the test instrument, the first tier system being programmable to perform testing operations on a device;
a second tier system comprising a plurality of embedded processing devices dedicated to device testing, the embedded devices being programmable to perform testing operations on the device; and
a third tier system that is programmed to act as an interface to the device, the third tier system being configurable to perform testing operations on the device, the first tier system and the second tier system being programmed to access the device through the interface;
wherein the third tier system defines at least a number of input ports and a number of output ports of the interface to the device;
wherein the second tier system is configured to transmit test results from the third tier system to the first tier system; and
wherein the third tier system is configurable to execute one or more of the testing operations separately of the second tier system;
wherein the first tier system has a first testing latency, the second tier system has a second testing latency, and the third tier system has a third testing latency, the first testing latency being greater than the second testing latency, and the second testing latency being greater than the third testing latency.

12. The test instrument of claim 11 , wherein the first testing latency is on the order of milliseconds, the second testing latency is on the order of microseconds, and the third testing latency is on the order of nanoseconds.

13. The test instrument of claim 11 , wherein the first tier system is programmed to run one or more test programs to perform the testing operations on the device;
wherein the second tier system is not programmed to run one or more test programs to perform the testing operations on the device; and
wherein the third tier system is not configured to perform one or more of the testing operations on the device.

14. The test instrument of claim 11 , wherein the first tier system is not programmed to run one or more test programs to perform the testing operations on the device;
wherein the second tier system is programmed to run one or more test programs to perform the testing operations on the device; and
wherein the third tier system is not configured to perform one or more testing operations on the device.

15. The test instrument of claim 11 , wherein the first tier system is not programmed to run one or more test programs to perform the testing operations on the device;
wherein the second tier system is not programmed to run one or more test programs to perform the testing operations on the device; and
wherein the third tier system is configured to perform one or more testing operations on the device.

16. The test instrument of claim 11 , wherein the first tier system comprises a processing device that executes a windowing operating system;
wherein each of the embedded processing devices is for testing a different device to be tested by the test instrument; and
wherein the third tier system comprises one or more field programmable gate arrays (FPGAs), each of the one or more FGPAs being for testing a different device to be tested by the test instrument.

17. The test instrument of claim 11 , wherein the third tier system comprises field programmable

Assignees

• Kaushansky David
• Frick Lloyd K
• Bourassa Stephen J
• Vandervalk David
• Fluet Michael Thomas
• Mcgoldrick Michael Francis
• Teradyne Inc

Inventors

• Kaushansky David
• Frick Lloyd K
• Bourassa Stephen J
• Vandervalk David
• Fluet Michael Thomas
• Mcgoldrick Michael Francis

Classifications

• G01R31/31908 Primary

  Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns · CPC title

• G01R31/31926

  Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing · CPC title