Method and integrated device for analyzing liquid flow and liquid-solid interface interaction

US9759643B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9759643-B2
Application numberUS-201615001321-A
CountryUS
Kind codeB2
Filing dateJan 20, 2016
Priority dateSep 30, 2014
Publication dateSep 12, 2017
Grant dateSep 12, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

An Integrated Circuit (IC) chip with a lab-on-a-chip, a method of manufacturing the lab-on-a-chip and a method of using the lab-on-a-chip for fluid flow analysis in physical systems through combination with computer modeling. The lab-on-a-chip includes cavities in a channel layer and a capping layer, preferably transparent, covering the cavities. Gates control two dimensional (2D) lattice structures acting as heaters, light sources and/or sensors in the cavities, or fluid channels. The gates and two dimensional (2D) lattice structures may be at the cavity bottoms or on the capping layer. Wiring connects the gates and the 2D lattice structures externally.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of analyzing fluid flow through a selected body, said method comprising: collecting data describing physical characteristics for a body; fabricating a lab-on-a-chip modeling said body from said data, fabricating said lab-on-a-chip comprising: opening one or more cavities in a channel layer, forming a capping layer for covering said one or more cavities, said capping layer being transparent, forming a two dimensional (2D) lattice structure at one surface of each of said one or more cavities, said 2D lattice structure being transparent, forming a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure, and forming wiring connecting the gates and the 2D lattice structures externally; adding fluid to said cavity; selectively connecting biases, signals and sensors to said wiring; causing light to pass through said fluid; measuring fluid flow responses to said biases, signals and light. 2. A method as in claim 1 , wherein said capping layer includes at least one input/output port above at least one cavity, said input/output port for introducing said fluid into, and removing said fluid from, said cavity. 3. A method as in claim 1 , wherein biasing said gates and said 2D lattice structures causes one or more of said 2D lattice structures to generate said light being measured to pass through said fluid. 4. A method as in claim 1 , wherein biasing said gates and said 2D lattice structures causes one or more of said 2D lattice structures to heats said fluid, an optical wave guide providing said light being measured to one surface of said lab-on-a-chip, said light exiting an opposite surface of said lab-on-a-chip to a detector at said opposite surface. 5. A method as in claim 1 , wherein said body is a hydrocarbon reservoir, said one or more cavities including one or more structural features representative of the physical properties of said hydrocarbon reservoir, said one or more structural features obstructing fluid flow through said cavity. 6. A method as in claim 1 , wherein at least one said 2D lattice structure is a local heater selectively heating said fluid at said at least one 2D lattice structure. 7. A method as in claim 1 , wherein said body is a biological body.

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Classifications

  • Earth materials (G01N33/42 takes precedence) · CPC title

  • G01N11/04Primary

    through a restricted passage, e.g. tube, aperture · CPC title

  • Floor-planning or layout, e.g. partitioning or placement · CPC title

  • thermally excited · CPC title

  • optical properties · CPC title

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What does patent US9759643B2 cover?
An Integrated Circuit (IC) chip with a lab-on-a-chip, a method of manufacturing the lab-on-a-chip and a method of using the lab-on-a-chip for fluid flow analysis in physical systems through combination with computer modeling. The lab-on-a-chip includes cavities in a channel layer and a capping layer, preferably transparent, covering the cavities. Gates control two dimensional (2D) lattice struc…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G01N11/04. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).