Package for housing electronic component and electronic device

Patent metadata

Field	Value
Publication number	US-9756731-B2
Application number	US-201414758334-A
Country	US
Kind code	B2
Filing date	Feb 25, 2014
Priority date	Feb 25, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A package for housing an electronic component, which is provided with: a substrate part that comprises an insulating substrate, which is formed of a ceramic sintered body and comprises a recess portion, and a wiring conductor which is provided on the insulating substrate; and a metal portion which is formed of a sintered body of a getter metal material and is directly bonded to the recess portion.

First claim

The invention claimed is:

1. A package for housing an electronic component, comprising:
an insulating substrate made from a ceramic sintered body, the insulating substrate comprising a recess portion, and a wiring conductor provided on the insulating substrate;
a metal portion made from a sintered body of a getter metal material directly bonded to the recess portion; and
a cavity portion provided on an inner surface of the recess portion, wherein the metal portion is positioned within the cavity portion and fills the cavity portion.

2. The package for housing an electronic component according to claim 1 , wherein the metal portion is accommodated in entirety within the cavity portion.

3. The package for housing an electronic component according to claim 1 , wherein the metal portion is provided so as to extend from inside the cavity portion to the inner surface of the recess portion.

4. The package for housing an electronic component according to claim 1 , wherein the inner surface of the recess portion comprises a side face and a bottom face, the side face comprising a step-shaped portion, and the cavity portion is provided on a side face of the step-shaped portion.

5. The package for housing an electronic component according to claim 4 , wherein the wiring conductor is provided on a top face of the step-shaped portion, the top face of the step-shaped portion is in a polygonal frame shape in a plane view, and the cavity portion is positioned in a corner of the top face in a plane view.

6. The package for housing an electronic component according to claim 1 , wherein the inner surface of the recess portion comprises a side face and a bottom face, and the metal portion is provided on the bottom face of the recess portion.

7. The package for housing an electronic component according to claim 6 , wherein the bottom face of the recess portion comprises a mounting portion for the electronic component, and the metal portion is provided on the bottom face of the recess portion and surrounds the mounting portion.

8. The package for housing an electronic component according to claim 1 , wherein the metal portion is directly bonded to the inner surface of the recess portion.

9. The package for housing an electronic component according to claim 8 , wherein in a vicinity of an interface between the metal portion and the inner surface of the recess portion, at least a component of either the metal portion or the inner surface of the recess portion is present in the other.

10. The package for housing an electronic component according to claim 1 , wherein the metal portion is directly bonded to a metallization layer provided on the inner surface of the recess portion.

11. The package for housing an electronic component according to claim 10 , wherein in a vicinity of an interface between the metal portion and the metallization layer, at least a component of either the metal portion or the metallization layer is present in the other.

12. An electronic device comprising:
the package for housing an electronic component according to claim 1 ; and
the electronic component housed within the recess portion.

Assignees

• Kyocera Corp

Inventors

• Niino Noritaka

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title