Chip-integrated through-plating of multi-layer substrates

Patent metadata

Field	Value
Publication number	US-9756730-B2
Application number	US-201113883154-A
Country	US
Kind code	B2
Filing date	Oct 21, 2011
Priority date	Nov 5, 2010
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A laminate and method for producing the laminate are provided for contacting at least one electronic component. An insulating layer is laminated between first and second metal layers electrically contacted to each other in at least one contact region. At least one recess in the contact region is generated with at least one embossing and/or bulging in the first metal layer. The distance between the two metal layers is reduced, such that dimensions of the embossing/bulging are sufficient for taking up the electronic component, which is inserted and connected into the embossing/bulging in a conductive manner therein. The electronic component is taken up in the embossing/bulging entirely with respect to its circumference and at least partly with respect to the height (H) of the electronic component. The laminate may be used as a circuit board, sensor, LED lamp, mobile phone component, control, or regulator.

First claim

We claim:

1. A method for producing a laminate for contacting at least one electronic component, the method comprising:
arranging an insulating layer between a first metal layer and a second metal layer,
electrically contacting the metal layers to each other in at least one contact region,
generating at least one recess in the at least one contact region in the insulating layer,
generating at least one embossing or bulging in the at least one contact region at least in the first metal layer, wherein a distance between the metal layers in regions of the at least one embossing or bulging is reduced, and
laminating the metal layers to the insulating layer,
wherein dimensions of the at least one embossing or bulging are sufficient for taking up at least one electronic component,
wherein at least one light emitting diode (LED) is inserted as the electronic component, and the at least one electronic component is inserted into the at least one embossing or bulging and is connected in conductive manner therein, such that the electronic component is taken up in the at least one embossing or bulging entirely with respect to a circumference of the electronic component and with respect to a height of the electronic component,
wherein the embossing or bulging is formed such that an angle of a side wall with respect to the first metal layer is established,
a surface of the at least one embossing or bulging is a reflective surface, produced by a stamp which is polished to be of optical quality, wherein the stamp produces a smooth surface of the embossing or bulging, and
wherein the first metal layer and the second metal layer at least partially touch each other.

2. The method according to claim 1 , wherein a cross-section of the at least one embossing or bulging is produced to be equal to or larger than dimensions of the at least one electronic component.

3. The method according to claim 2 , wherein the cross-section of the at least one embossing or bulging is produced to be at least equal to a cross-section of the at least one electronic component perpendicular to the height.

4. The method according to claim 1 , wherein the metal layers are connected to the insulating layer by punch-lamination which concurrently produces the at least one embossing or bulging.

5. The method according to claim 1 , wherein the at least one embossing or bulging in the first metal layer is positioned in at least one pre-existing recess in the insulating layer.

6. The method according to claim 1 , wherein the at least one embossing or bulging comprises at least one passage in the first metal layer or at least one passage is produced in the at least one embossing or bulging, wherein each passage breaks through a surface of the first metal layer.

7. The method according to claim 1 , wherein the at least one embossing or bulging in the first metal layer is produced in a same step in which the electronic component is contacted to the first metal layer.

8. The method according to claim 1 , wherein the light from the at least one embossing or bulging is emitted in a direction perpendicular to a major plane of the first metal layer.

9. The method according to claim 1 , wherein at least one region of the first metal layer is separated such that at least two regions of the first metal layer are arranged next to each other spaced from each other and electrically insulated from each other, and wherein the at least one electronic component is connected to at least two regions in a conductive manner.

10. The method according to claim 9 , wherein the at least one electronic component is connected to the at least two regions by at least one bonding wire such that applying a voltage between the two regions leads to an electrical current being conducted through the electronic component.

Assignees

• Klein Andreas Steffen
• Ditzel Eckhard
• Krüger Frank
• Schumann Michael
• Osram Opto Semiconductors Gmbh

Inventors

• Klein Andreas Steffen
• Ditzel Eckhard
• Krüger Frank
• Schumann Michael

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/931

  Shapes of bond pads · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title