Receiver for wireless communication network with extended range

Patent metadata

Field	Value
Publication number	US-9755785-B2
Application number	US-27183608-A
Country	US
Kind code	B2
Filing date	Nov 14, 2008
Priority date	Jun 1, 2005
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Techniques for detecting and demodulating a signal/transmission are described. Signal detection is performed in multiple stages using different types of signal processing, e.g., using time-domain correlation for a first stage, frequency-domain processing for a second stage, and time-domain processing for a third stage. For the first stage, products of symbols are generated for at least two different delays, correlation between the products for each delay and known values is performed, and correlation results for all delays are combined and used to declare the presence of a signal. For demodulation, the timing of input samples is adjusted to obtain timing-adjusted samples. A frequency offset is estimated and removed from the timing-adjusted samples to obtain frequency-corrected samples, which are processed with a channel estimate to obtain detected symbols. The phases of the detected symbols are corrected to obtain phase-corrected symbols, which are demodulated, deinterleaved, and decoded.

First claim

What is claimed is:

1. An apparatus comprising:
a processor operative to remove a frequency offset in input samples to obtain frequency-corrected samples, to process the frequency-corrected samples with a channel estimate to obtain detected symbols, to correct phases of the detected symbols to obtain phase-corrected symbols, and to perform demodulation on the phase-corrected symbols to obtain demodulated symbols; and
a memory coupled to the processor.

2. The apparatus of claim 1 , wherein the processor is operative to adjust timing of the input samples to obtain timing-adjusted samples and to remove the frequency offset in the timing-adjusted samples to obtain the frequency-corrected samples.

3. The apparatus of claim 2 , wherein the processor is operative to filter the input samples with a polyphase filter to adjust the timing of the input samples.

4. The apparatus of claim 1 , wherein the processor is operative to determine a timing adjustment based on the frequency offset, to adjust timing of the input samples based on the timing adjustment to obtain timing-adjusted samples, and to remove the frequency offset in the timing-adjusted samples to obtain the frequency-corrected samples.

5. The apparatus of claim 1 , wherein the processor is operative to derive a first set of channel taps based on a first set of symbols, to derive a second set of channel taps based on a second set of symbols, to determine a phase difference between the first and second sets of channel taps, to estimate a residual frequency error based on the phase difference, and to remove the residual frequency offset from the input samples.

6. The apparatus of claim 5 , wherein the first set of symbols is for a first portion of a SYNC field carrying a pilot, and wherein the second set of symbols is for a second portion of the SYNC field.

7. The apparatus of claim 5 , wherein the processor is operative to generate products of the channel taps in the first set with complex conjugate of the channel taps in the second set, and to sum the products to determine the phase difference between the first and second sets of channel taps.

8. The apparatus of claim 7 , wherein the processor is operative to perform thresholding on the channel taps in the first and second sets, or on the products, or on both the channel taps and the products.

9. The apparatus of claim 1 , wherein the processor is operative to rotate each detected symbol by a phase reference to obtain a corresponding phase-corrected symbol.

10. The apparatus of claim 9 , wherein the processor is operative to update the phase reference based on phases of the detected symbols.

11. The apparatus of claim 1 , wherein the processor is operative to deinterleave the demodulated symbols and to decode deinterleaved symbols to obtain decoded data.

12. A method of receiving a transmission, comprising:
removing a frequency offset in input samples to obtain frequency-corrected samples;
processing the frequency-corrected samples with a channel estimate to obtain detected symbols;
correcting phases of the detected symbols to obtain phase-corrected symbols; and
performing demodulation on the phase-corrected symbols to obtain demodulated symbols.

13. The method of claim 12 , further comprising:
determining a timing adjustment based on the frequency offset; and
adjusting timing of the input samples based on the timing adjustment to obtain timing-adjusted samples, and wherein the frequency offset is removed from the timing-adjusted samples to obtain the frequency-corrected samples.

14. The method of claim 12 , further comprising:
deriving a first set of channel taps based on a first set of symbols;
deriving a second set of channel taps based on a second set of symbols;
determining a phase difference between the first and second sets of channel taps;
estimating a residual frequency error based on the phase difference; and
removing the residual frequency offset from the input samples.

15. The method of claim 12 , wherein the correcting the phases of the detected symbols comprises
rotating each detected symbol by a phase reference to obtain a corresponding phase-corrected symbol, and updating the phase reference based on phases of the detected symbols.

16. An apparatus comprising:
means for removing a frequency offset in input samples to obtain frequency-corrected samples;
means for processing the frequency-corrected samples with a channel estimate to obtain detected symbols;
means for correcting phases of the detected symbols to obtain phase-corrected symbols; and
means for performing demodulation on the phase-corrected symbols to obtain demodulated symbols.

17. The apparatus of claim 16 , further comprising:
means for determining a timing adjustment based on the frequency offset and adjusting timing of the input samples based on the timing adjustment to obtain timing-adjusted samples,
wherein the means for removing the frequency offset is configured to remove the frequency offset from the timing-adjusted samples to obtain the frequency-corrected samples.

18. The apparatus of claim 16 , further comprising:
means for deriving a first tap channel estimate based on a first set of symbols, deriving a second tap channel estimate based on a second set of symbols, determining a phase difference between the first and second tap channel estimates, and estimating a residual frequency error based on the phase difference,
wherein the means for removing the frequency offset is configured to remove the residual frequency offset from the input samples.

19. The apparatus of claim 16 , wherein the means for correcting the phases of the detected symbols is configured to:
rotate each detected symbol by a phase reference to obtain a corresponding phase-corrected symbol, and
update the phase reference based on phases of the detected symbols.

20. An apparatus used when receiving a transmission comprising a memory unit having instructions stored thereon, the instructions being executable by one or more processors and the instructions comprising:
instructions for removing a frequency offset in input samples to obtain frequency-corrected samples;
instructions for processing the frequency-corrected samples with a channel estimate to obtain detected symbols;
instructions for correcting phases of the detected symbols to obtain phase-corrected symbols; and
instructions for performing demodulation on the phase-corrected symbols to obtain demodulated symbols.

21. The apparatus of claim 20 , further comprising:
instructions for determining a timing adjustment based on the frequency offset; and
instructions for adjusting timing of the input samples based on the timing adjustment to obtain timing-adjusted samples, and wherein the frequency offset is removed from the timing-adjusted samples to obtain the frequency-corrected samples.

22. The apparatus of claim 20 , further comprising:
instructions for deriving a first set of channel taps based on a first set of symbols;
instructions for deriving a second set of channel taps based on a second set of symbols;
instructions for determining a phase difference between the first and second sets of channel taps;
instructions for estimating a residual frequency error based on the phase difference; and
instructions for removing the residual frequency offset from the input samples.

23. The apparatus of claim 20 , wherein the instructions for correcting the phases of the detected symbols comprise:
instruc

Assignees

• Walton J Rodney
• Wallace Mark S
• Qualcomm Inc

Inventors

• Walton J Rodney
• Wallace Mark S

Classifications

• H04B1/7073

  Synchronisation aspects · CPC title

• H04L2027/0065

  Frequency error detectors (H04L2027/0067 takes precedence) · CPC title

• H04L1/0072 Primary

  Error control for data other than payload data, e.g. control data · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title

• H04L27/0014

  Carrier regulation (of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657) · CPC title