Current source logic gate

Patent metadata

Field	Value
Publication number	US-9755645-B1
Application number	US-201615373689-A
Country	US
Kind code	B1
Filing date	Dec 9, 2016
Priority date	Dec 11, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

First claim

The invention claimed is:

1. An apparatus configured to create digital logic gates, comprising:
a first N channel depletion mode field effect transistor (“first transistor”) with gate, source, and drain terminals, wherein the gate terminal acts as an input to the apparatus; and
a second N channel depletion mode field effect transistor (“second transistor”) with gate, source, and drain terminals, configured as a current source, wherein
the drain terminal of the second transistor is tied to a positive voltage relative to ground,
the source terminal of the first transistor tied to ground and the drain terminal of the first transistor tied through a first resistor to the source terminal of the second transistor and directly to the gate terminal of the second transistor,
and
the drain of the first transistor is further tied to a second resistor in series with a third resistor, a remaining lead of the third resistor is tied to a negative voltage relative to ground, and a node common to the second and third resistors is the output of the apparatus.

2. The apparatus of claim 1 , wherein the first, second and third resistors are selected based on transfer functions or functional parameters of the first and second transistors such that for a logic false input to the apparatus, a logic true output appears at the output of the apparatus, or for a logic true input to the apparatus, a logic false output appears at the output of the apparatus.

3. The apparatus of claim 1 , wherein the first transistor is replaced by n N channel depletion mode field effect transistor in series to create a logical NAND structure at the input of the apparatus.

4. The apparatus of claim 1 , wherein the first transistor is replaced by m N channel depletion mode field effect transistor in parallel to create a logical NOR structure at the input of the apparatus.

5. The apparatus of claim 1 , wherein the first transistor is a combination of n series N channel depletion mode field effect transistors and m parallel N channel depletion mode field effect transistors to create multiple term sum of products logic functions.

6. The apparatus of claim 1 , wherein a positive voltage and a negative voltage relative to ground are selected to accommodate a turn off voltage of the first transistor as reflected by a voltage divider function performed by the second and third resistors.

7. The apparatus of claim 6 , wherein a value of the first resistor is selected to set a current output of the second transistor,
the current output is further selected in accordance with selected positive voltage and negative voltage and to define a value for the second resistor and a value for the third resistor.

8. A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors, comprising:
a current source comprising a transistor and a current source resistor;
a current steering switch input stage comprising a transistor to steer current to set an output stage bias point depending on an input logic signal state; and
a resistor divider level shifting output stage comprising a first resistor and a second resistor to set the output stage point and produce valid output logic signal states, wherein
the transistor of the current steering switch input stage functions as a switch to provide at least two operating points.

9. The current source logic gate of claim 8 , wherein the two operating points comprises a logic level high and a logic level low.

10. The current source logic gate of claim 9 , wherein,
when the operating point comprises the logic level high at the input stage of the current steering switch, a logic low output appears at an output stage of the current source logic gate, or
when the operating point comprises the logic level low at the input stage of the current steering switch, a logic high output appears at the output stage of the current source logic gate.

11. The current source logic gate of claim 8 , wherein the current steering switch input stage comprises one or more additional transistors connected in parallel, in series, or both.

12. The current source logic gate of claim 8 , wherein the current steering switch input stage acts as a switch to limit logic gate current.

13. The current source logic gate of claim 8 , wherein the current source resistor of the current source controls current provided by the current source.

14. A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors, comprising:
a first N channel depletion mode FET (“first transistor”) with gate, source, and drain terminals; and
a second N channel depletion mode FET (“second transistor”) with gate, source, and drain terminals, wherein
the first transistor is configured to act as a current source, and is positioned above the second transistor,
the drain terminal of the first transistor is tied to a positive voltage relative to ground,
the gate terminal of the second transistor acts as an input to the current source logic gate,
the source terminal of the second transistor is tied to ground, and the drain terminal of the second transistor is tied through a first resistor to the source terminal of the first transistor and directly to the gate terminal of the first transistor, and
the drain of the second transistor is further tied to a second resistor in series with a third resistor, a remaining lead of the third resistor is tied to a negative voltage relative to ground, and a node common to the second and third resistors is the output of the current source logic gate.

15. The current source logic gate of claim 14 , wherein the first resistor, the second resistor, and the third resistor are selected based on transfer functions or functional parameters of the first and second transistors such that for a logic false input to the current source logic gate, a logic true output appears at the output of the current source logic gate, or for a logic true input to the current source logic gate, a logic false output appears at the output of the current source logic gate.

16. The current source logic gate of claim 14 , wherein the second transistor is replaced by n N channel depletion mode field effect transistor in series to create a logical NAND structure at the input of the current source logic gate.

17. The current source logic gate of claim 14 , wherein the second transistor is replaced by m N channel depletion mode field effect transistor in parallel to create a logical NOR structure at the input of the current source logic gate.

18. The current source logic gate of claim 14 , wherein the second transistor is a combination of n series N channel depletion mode field effect transistors and m parallel N channel depletion mode field effect transistors to create multiple term sum of products logic functions.

19. The current source logic gate of claim 14 , wherein a positive voltage and a negative voltage relative to ground are selected to accommodate a turn off voltage of the second transistor as reflected by a voltage divider function performed by the second and third resistors.

20. The current source logic gate of claim 19 , wherein a value of the first resistor is selected to set a current output of the first transistor,
the current output is further selected in accordance with selected positive voltage and negative voltage and to define a value for the second resistor and a value for the third resistor.

Assignees

• Nasa
• The Us Administrator Of Nat Aeronautics And Space Administration

Inventors

• Krasowski Michael J
• Prokop Norman F

Classifications

• H03K19/09407

  of the same canal type · CPC title

• H03K19/0952 Primary

  using Schottky type FET {MESFET}({H03K19/09421, H03K19/09432}, H03K19/096 take precedence) · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/09403

  using junction field-effect transistors (H03K19/096 takes precedence) · CPC title