Charge shedding circuit

Patent metadata

Field	Value
Publication number	US-9755514-B2
Application number	US-201514793147-A
Country	US
Kind code	B2
Filing date	Jul 7, 2015
Priority date	Mar 20, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

In one embodiment, a method receives a shed comparison signal that is based on a comparison of a voltage detected from a voltage converter to a reference voltage and receives a zero cross signal that indicates whether a current from the voltage converter has crossed zero. The shed comparison signal is sampled for a first number of clock cycles to generate shed comparison sampled values. Also, the zero cross signal is sampled for a second number of clock cycles to generate zero cross sampled values where the second number of clock cycles are less than the first number of clock cycles. The method determines a change between a shed state and an unshed state based on the shed comparison sampled values for the first number of clock cycles or the zero cross sampled values for the second number of clock cycles.

First claim

What is claimed is:

1. A voltage converter comprising:
a switching logic including a plurality of transistors, wherein a portion of the plurality of transistors are configured to be switched on and off when the voltage converter changes between a shed state and an unshed state;
a first comparison logic configured to compare a voltage from the voltage converter to a reference voltage, the first comparison logic configured to generate a shed comparison signal based on a comparison of the voltage from the voltage converter to the reference voltage;
a second comparison logic configured to determine whether a current from the voltage converter has crossed zero and generate a zero cross signal that indicates the current from the voltage converter has crossed zero;
a first ripple counter logic configured to sample the shed comparison signal for a first number of clock cycles to generate shed comparison sampled values;
a second ripple counter logic configured to sample the zero cross signal for a second number of clock cycles to generate zero cross sampled values, wherein the second number of clock cycles are less than the first number of clock cycles; and
a shed signal logic configured to determine a change between the shed state and the unshed state corresponding to the portion of the plurality of transistors based on monitoring the shed comparison sampled values for the first number of clock cycles and the zero cross sampled values for the second number of clock cycles to determine either the shed comparison sampled values have essentially a first same value or the zero cross sampled values have essentially a second same value.

2. The voltage converter of claim 1 , further comprising:
a selection logic configured to turn on or turn off the portion of the plurality of transistors based on a shed signal generated by the shed signal logic indicating the change between the shed state and the unshed state.

3. The voltage converter of claim 1 , wherein:
the plurality of transistors includes a first set of high side transistors of a first type and a second set of low side transistors of a second type,
wherein the first comparison logic is coupled to a transistor in the second set of low side transistors, and
wherein the voltage from the voltage converter is a voltage across the transistor in the second set of low side transistors.

4. The voltage converter of claim 1 , wherein:
the first ripple counter logic comprises a first counter including a first delay, and
the second ripple counter logic comprises a second counter including a second delay shorter than the first delay.

5. The voltage converter of claim 1 , wherein the shed signal logic comprises:
a set-reset latch configured to determine the change between the shed state and the unshed state based on determining the shed comparison sampled values are essentially the first same value for the first number of clock cycles or determining the zero cross sampled values are essentially the second same value for the second number of clock cycles.

6. The voltage converter of claim 1 , further comprising:
a first current limit logic configured to generate a current limit signal when a current limit is detected in the voltage converter, wherein the current limit is detected when the current goes above a current limit threshold; and
a second current limit logic configured to use the current limit signal to change the voltage converter from the shed state to the unshed state.

7. The voltage converter of claim 6 , further comprising:
a blanking logic configured to blank the current limit signal for a time delay after the current limit signal changes the voltage converter from the shed state to the unshed state.

8. The voltage converter of claim 7 , wherein the blanking logic uses a delayed voltage from a transistor in the plurality of transistors to perform the blanking.

9. The voltage converter of claim 6 , further comprising:
a pulse width modulation (PWM) logic configured to blank a PWM comparison signal that is configured to turn off high side transistors from the plurality of transistors, the PWM logic using the current limit signal to blank the PWM comparison signal for a time delay while the voltage converter changes between the shed state and the unshed state.

10. The voltage converter of claim 1 , wherein:
the switching logic includes a first set of high side transistors and a second set of low side transistors,
the first comparison logic includes a first comparator coupled to a transistor in the second set of low side transistors configured to compare a voltage across the transistor to the reference voltage, the comparator configured to generate the shed comparison signal that indicates whether the voltage across the transistor has crossed the reference voltage,
the second comparison logic includes a second comparator configured to determine whether the current from the transistor has crossed zero and to generate the zero cross signal that indicates the current has crossed zero,
the first ripple counter logic includes a first counter configured to sample the shed comparison signal for the first number of clock cycles to generate the shed comparison sampled values,
the second ripple counter logic includes a second counter configured to sample the zero cross signal for the second number of clock cycles to generate the zero cross sampled values, and
the shed signal logic includes a set-reset latch configured to determine the change between the shed state and the unshed state based on the shed comparison sampled values for the first number of clock cycles or based on the zero cross sampled values for the second number of clock cycles.

11. The voltage converter of claim 10 , further comprising:
a reference generator logic configured to adjust the reference voltage for temperature changes.

12. A method comprising:
generating, by a voltage converter, a shed comparison signal that is based on a comparison of a voltage detected from a voltage converter to a reference voltage;
generating, by the voltage converter, a zero cross signal that indicates whether a current from the voltage converter has crossed zero;
sampling the shed comparison signal for a first number of clock cycles to generate shed comparison sampled values;
sampling the zero cross signal for a second number of clock cycles to generate zero cross sampled values, wherein the second number of clock cycles are less than the first number of clock cycles;
monitoring the shed comparison sampled values for the first number of clock cycles and the zero cross sampled values for the second number of clock cycles; and
causing a change between a shed state and an unshed state corresponding to a portion of a plurality of transistors of the voltage converter based on determining either the shed comparison sampled values have essentially a first same value or the zero cross sampled values have essentially a second same value.

13. The method of claim 12 , wherein:
sampling the shed comparison signal comprises delaying the shed comparison signal by a first delay before determining the shed comparison sampled values, and
sampling the zero cross signal comprises delaying the zero cross signal by a second delay before determining the shed comparison sampled values, the second delay being less than the first delay.

14. The method of claim 12 , wherein:
determining the change between the shed state and the unshed state based on the shed comparison sampled values comprises determining the shed comparison sampled values are below the same value threshold for the first number of clock cycles, and
determining the change be

Assignees

• Qualcomm Inc

Inventors

• Pullen Stuart
• Rader William

Classifications

• Y02B70/16

  Cross-Sectional Technologies · mapped topic

• Y02B70/1466

  Cross-Sectional Technologies · mapped topic

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/1588

  comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title