Asymmetric correlated electron switch operation

Patent metadata

Field	Value
Publication number	US-9755146-B2
Application number	US-201514850213-A
Country	US
Kind code	B2
Filing date	Sep 10, 2015
Priority date	Sep 10, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Subject matter disclosed herein may relate to correlated electron switches that are capable of asymmetric set or reset operations.

First claim

What is claimed is:

1. A correlated electron switch (CES) device comprising:
first and second terminals; and
a portion of a correlated electron material (CEM) substrate coupled between the first and second terminals, wherein the CEM substrate is non-uniformly doped between the first and second terminals, and at least a portion of the CEM substrate intrinsic,
wherein the CES is capable of being placed in a conductive or low impedance state responsive to a first or second set operation, or an insulative or high impedance memory state responsive to a first or second reset operation, and
wherein the first set operation is asymmetric with the second set operation.

2. The CES device of claim 1 , and wherein:
the first set operation is characterized by a first set voltage condition and a first set current condition across the first and second terminals,
the second set operation is characterized by a second set voltage condition and a second set current condition across the first and second terminals,
a polarity of the first set voltage condition is opposite a polarity of the second set voltage condition, and
a magnitude of the first set voltage condition is greater than a magnitude of the second set voltage condition.

3. The CES device of claim 2 , wherein a polarity of the first set current condition is opposite a polarity of the second set current condition, and wherein a magnitude of the first set current condition is greater than a magnitude of the second set current condition.

4. The CES device of claim 1 , wherein the first reset operation is asymmetric with the second reset operation.

5. The CES device of claim 4 , wherein the first reset operation is characterized by a first reset voltage condition and a first reset current condition across the first and second terminals, and the second reset condition is characterized by a second reset voltage condition and a second reset current condition across the first and second terminals, and
wherein a polarity of the first reset voltage condition is opposite a polarity of the second reset voltage condition, and wherein a magnitude of the first reset voltage condition is greater than a magnitude of the second reset voltage condition.

6. The CES device of claim 5 , wherein a polarity of the first reset current condition is opposite a polarity of the second reset current condition, and wherein a magnitude of the first reset current condition is greater than a magnitude of the second reset current condition.

7. The CES device of claim 1 , wherein the CES device is configurable to be in the conductive or low impedance state, or the insulative or high impedance state based, at least in part, on a screening length of CEM of the CEM substrate and responsive to localization properties of electrons in the CEM.

8. A method comprising:
forming first and second terminals on at least a portion of a correlated electron material (CEM) substrate to form a correlated electron switch (CES), wherein the CES is capable of being placed in a conductive or low impedance state responsive to a first or second set operation, or an insulative or high impedance memory state responsive to a first or second reset operation;
maintaining at least a portion of the CEM substrate intrinsic; and
affecting a structure or composition of the CEM substrate such that the first set operation is asymmetric with the second set operation by applying a P-type doping or an N-type doping over at least a portion of the CEM substrate.

9. The method of 8 , wherein the CEM substrate comprises a transition metal oxide.

10. The method of claim 8 , wherein affecting the structure or composition of the CEM substrate further affects the structure or composition of the CEM substrate such that the first reset operation is asymmetric with the second reset operation.

11. The method of claim 8 , wherein affecting the structure or composition of the CEM substrate further comprises affecting a concentration of doping over at least a portion of the CEM substrate according to a gradient.

12. The method of claim 8 , wherein the CES is configurable to be in the conductive or low impedance state, or the insulative or high impedance state based, at least in part, on a screening length of CEM of the CEM substrate and responsive to localization properties of electrons in the CEM.

Assignees

• Advanced Risc Mach Ltd
• Advanced Risc Mach Ltd

Inventors

• Shifren Lucian
• Yeric Greg

Classifications

• G11C13/0007 Primary

  comprising metal oxide memory material, e.g. perovskites · CPC title

• H01L45/146

  Electricity · mapped topic

• G11C2213/73

  Array where access device function, e.g. diode function, being merged with memorizing function of memory element · CPC title

• H01L45/04

  Electricity · mapped topic

• G11C13/0069

  Writing or programming circuits or methods · CPC title