Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9755085-B2
Application number	US-201213537650-A
Country	US
Kind code	B2
Filing date	Jun 29, 2012
Priority date	Jul 8, 2011
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

First claim

What is claimed is:

1. A semiconductor device, comprising:
memory blocks each configured to comprise a pipe gate and channels, each channel including a pipe channel formed in the pipe gate and a pair of a drain-side channel and a source-side channel coupled to the pipe channel;
insulating layers placed between the memory blocks adjacent to other memory blocks, and interposed between pipe gates of the memory blocks to insulate the pipe gates from each other;
first slits placed between the memory blocks adjacent to other memory blocks and placed above the insulating layers; and
a second slit placed between the source-side channel and the drain-side channel of each pair of channels;
third slits placed between the drain-side channels adjacent to other drain-side channels and formed to generally the same depth as drain select lines, wherein the drain select lines of the drain-side channels adjacent to other drain-side channels are separated from each other by the third slits interposed therebetween, and the drain-side channels adjacent to each other share a drain-side word line; and
fourth slits placed between the source-side channels adjacent to other source-side channels and formed to generally the same depth as source select lines, wherein the source select lines of the source-side channels adjacent to other source-side channels are separated from each other by the fourth slits interposed therebetween, and the source-side channels adjacent to each other share a source-side word line.

2. The semiconductor device of claim 1 , wherein the channels arranged in one direction form each of a channel row, and the channel row arranged generally in a zigzag and coupled to at least two bit lines.

3. The semiconductor device of claim 1 , wherein the first slits are located over the insulating layers.

4. The semiconductor device of claim 1 , wherein each of the first slits overlaps each of the insulating layers.

5. A semiconductor device, comprising:
memory blocks each configured to comprise a pipe gate and channels, each channel including a pipe channel formed in the pipe gate and a pair of a drain-side channel and a source-side channel coupled to the pipe channel;
insulating layers placed between the memory blocks adjacent to other memory blocks, and interposed between pipe gates of the memory blocks to insulate the pipe gates from each other;
first slits placed between the memory blocks adjacent to other memory blocks and placed above the insulating layers;
a second slit placed between the source-side channel and the drain-side channel of each pair of channels;
third slits placed between the drain-side channels adjacent to other drain-side channels, wherein a drain-side word line and a drain select line of the drain-side channels adjacent to other drain-side channels are separated from each other by the third slits interposed therebetween; and
fourth slits placed between the source-side channels adjacent to other source-side channels and formed to generally the same depth as source select lines, wherein the source select lines of the source-side channels adjacent to other source-side channels are separated from each other by the fourth slits interposed therebetween and the source-side channels adjacent to each other share a source-side word line.

6. A semiconductor device, comprising:
memory blocks each configured to comprise a pipe gate and channels, each channel including a pipe channel formed in the pipe gate and a pair of a drain-side channel and a source-side channel coupled to the pipe channel;
insulating layers placed between the memory blocks adjacent to other memory blocks, and interposed between the pipe gates of the memory blocks to insulate the pipe gates from each other;
first slits placed between the memory blocks adjacent to other memory blocks and placed above the insulating layers;
a second slit placed between the source-side channel and the drain-side channel of each pair of channels;
third slits placed between the source-side channels adjacent to other source-side channels, wherein a source-side word line and a source select line of the adjacent channels are separated from each other by the third slits interposed therebetween; and
fourth slits placed between the drain-side channels adjacent to other drain-side channels and formed to generally the same depth as drain select lines, wherein the drain select lines of the drain-side channels adjacent to other drain-side channels are separated from each other by the fourth slits interposed therebetween,
wherein the drain-side channels adjacent to each other share a drain-side word line.

7. A semiconductor device, comprising:
memory blocks each configured to comprise a pipe gate and channels, each channel including a pipe channel formed in the pipe gate and a pair of a drain-side channel and a source-side channel coupled to the pipe channel;
insulating layers placed between the memory blocks adjacent to other memory blocks, and interposed between the pipe gates of the memory blocks to insulate the pipe gates from each other;
first slits placed between the memory blocks adjacent to other memory blocks and placed above the insulating layers;
a second slit placed between the source-side channel and the drain-side channel of each pair of channels; and
at least one fifth slit placed substantially within a slimming region of the memory block, generally in a circumference of the slimming region, or substantially within the slimming region and generally in the circumference of the slimming region, wherein the memory block includes a cell region where the channels are located and the slimming region located at both sides of the cell region.

8. The semiconductor device of claim 7 , further comprising at least one of first contact pads formed generally at edges on both sides of the slimming region and second contact pads formed generally within the slimming region.

9. The semiconductor device of claim 7 , wherein the at least one fifth slit is formed generally within the slimming region of the memory block and configured to generally have a line form extended in parallel in one direction.

10. The semiconductor device of claim 7 , wherein the at least one fifth slit is formed generally within the slimming region of the memory block and configured to generally have a line form including protruding parts.

11. The semiconductor device of claim 7 , wherein the at least one fifth slit is placed generally within the slimming region of the memory block and each configured to include a first line pattern generally extended in a first direction and second line patterns generally extended in parallel in a second direction substantially crossing the first direction.

12. The semiconductor device of claim 7 , wherein the at least one fifth slit is placed generally within the slimming region of the memory block and configured to generally have a line form substantially crossing a boundary of the adjacent memory blocks.

13. The semiconductor device of claim 7 , wherein the at least one fifth slit is placed substantially between one of the first slits and a slimming region.

14. A semiconductor device, comprising:
a substrate including a source line therein;
memory blocks each configured to include channels coupled to the source line and protruded from the substrate, wherein each of the memory blocks includes a cell region where the channels are located and a slimming region located at both sides of the cell region, and the cell region and the slimming region are arranged in a direction parallel to a surface of the substrate;
at least one first slit placed in the slimming region of the memory

Assignees

• Lee Ki Hong
• Pyi Seung Ho
• Chang Jung Yun
• Sk Hynix Inc

Inventors

• Lee Ki Hong
• Pyi Seung Ho
• Chang Jung Yun

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic

• H01L29/7926 Primary

  Electricity · mapped topic