Bipolar junction transistor structure for reduced current crowding

Patent metadata

Field	Value
Publication number	US-9755018-B2
Application number	US-201113323297-A
Country	US
Kind code	B2
Filing date	Dec 12, 2011
Priority date	Dec 12, 2011
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.

First claim

What is claimed is:

1. A bipolar junction transistor comprising:
a collector;
a base region formed over the collector such that a bottom surface of the base region contacts the collector, the base region comprising:
an extrinsic base region;
an intrinsic base region that extends above the extrinsic base region to provide a mesa, the mesa comprising a top surface opposite the collector; and
a recess in the top surface of the mesa and comprising sidewalls that extend into the intrinsic base region to define a lateral boundary of the recess; and

an emitter formed over the top surface of the mesa and in the recess such that the emitter contacts the sidewalls of the recess.

2. The bipolar junction transistor of claim 1 wherein the emitter is essentially only formed over the mesa such that essentially none of the emitter is formed over the extrinsic base region.

3. The bipolar junction transistor of claim 1 wherein the intrinsic base region is directly laterally adjacent to the extrinsic base region.

4. The bipolar junction transistor of claim 1 wherein the intrinsic base region comprises an upper portion and a lower portion residing below the upper portion, the upper portion is intentionally doped with a first dopant at a first concentration, and the lower portion is intentionally doped with the first dopant at a second concentration that is intentionally different than the first concentration.

5. The bipolar junction transistor of claim 4 wherein the first concentration is higher than the second concentration.

6. The bipolar junction transistor of claim 4 wherein the first concentration is at least two times higher than the second concentration.

7. The bipolar junction transistor of claim 4 wherein the first concentration is between about two and ten times higher than the second concentration.

8. The bipolar junction transistor of claim 4 wherein the first concentration is around about five times higher than the second concentration.

9. The bipolar junction transistor of claim 1 wherein the sidewalls are substantially vertical.

10. The bipolar junction transistor of claim 1 wherein the collector, the intrinsic base region, the extrinsic base region, and the emitter comprise silicon carbide.

11. The bipolar junction transistor of claim 1 further comprising a silicon carbide substrate over which the collector is formed.

12. The bipolar junction transistor of claim 1 further comprising at least one base cap region formed between at least one base ohmic contact and the extrinsic base region, an emitter cap region formed over the emitter, and an emitter ohmic contact formed over the emitter cap region.

13. The bipolar junction transistor of claim 1 wherein the intrinsic base region has a first nominal thickness, the extrinsic base region has a second nominal thickness, the mesa has a mesa thickness equal to a difference between the first nominal thickness and the second nominal thickness, and wherein the mesa thickness is at least ten percent of the first nominal thickness.

14. The bipolar junction transistor of claim 13 wherein the mesa thickness is between about ten percent and seventy percent of the first nominal thickness.

15. The bipolar junction transistor of claim 13 wherein the mesa thickness is between about twenty percent and seventy percent of the first nominal thickness.

16. The bipolar junction transistor of claim 13 wherein the mesa thickness is between about thirty percent and seventy percent of the first nominal thickness.

17. The bipolar junction transistor of claim 13 wherein the mesa thickness is between about forty percent and seventy percent of the first nominal thickness.

18. The bipolar junction transistor of claim 13 wherein the mesa thickness is between about thirty-five percent and sixty percent of the first nominal thickness.

19. A method for forming a bipolar junction transistor comprising:
providing at least one collector layer for a collector;
forming at least one base layer over the at least one collector layer to provide an intrinsic base region and an extrinsic base region;
forming at least one emitter layer over the at least one base layer;
etching through a portion of the at least one emitter layer and substantially into the extrinsic base region, such that the intrinsic base region extends above the extrinsic base region to provide a mesa on which an emitter from the at least one emitter layer is formed, wherein a top surface of the mesa has a recess comprising sidewalls that extend downward into the intrinsic base region to define a lateral boundary of the recess, and the emitter layer contacts the sidewalls of the recess.

20. The method of claim 19 wherein the emitter is essentially only formed over the mesa such that essentially none of the emitter is formed over the extrinsic base region.

21. The method of claim 19 wherein the intrinsic base region is directly laterally adjacent to the extrinsic base region.

22. The method of claim 19 wherein the intrinsic base region comprises an upper portion and a lower portion residing below the upper portion, the upper portion is intentionally doped with a first dopant at a first concentration, the lower portion is intentionally doped with the first dopant at a second concentration that is intentionally different than the first concentration.

23. The method of claim 22 wherein the first concentration is higher than the second concentration.

24. The method of claim 19 wherein the collector, the intrinsic base region, the extrinsic base region, and the emitter comprise silicon carbide.

25. The method of claim 19 wherein the intrinsic base region has a first nominal thickness, the extrinsic base region has a second nominal thickness, the mesa has a mesa thickness equal to a difference between the first nominal thickness and the second nominal thickness, and wherein the mesa thickness is at least ten percent of the first nominal thickness.

26. A bipolar junction transistor comprising:
a collector;
a base region formed over the collector and comprising an extrinsic base region and an intrinsic base region that extends above the extrinsic base region to provide a mesa, the intrinsic base region having a top surface including a recess with sidewalls that extend downward into the intrinsic base region, wherein the sidewalls are substantially angled relative to an epitaxial plane of the bipolar junction transistor; and
an emitter formed over the mesa such that the emitter contacts the sidewalls of the recess.

27. The bipolar junction transistor of claim 26 wherein the emitter is essentially only formed over the intrinsic base region such that essentially none of the emitter is formed over the extrinsic base region.

28. The bipolar junction transistor of claim 26 wherein the intrinsic base region is directly laterally adjacent to the extrinsic base region.

29. The bipolar junction transistor of claim 26 wherein the intrinsic base region comprises an upper portion and a lower portion residing below the upper portion, the upper portion is intentionally doped with a first dopant at a first concentration, and the lower portion is intentionally doped with the first dopant at a second concentration that is intentionally different than the first dopant concentration.

30. The bipolar junction transistor of claim 29 wherein the first

Assignees

• Cheng Lin
• Agarwal Anant K
• Ryu Sei-Hyung
• Cree Inc

Inventors

• Cheng Lin
• Agarwal Anant K
• Ryu Sei-Hyung

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/8303

  Diamond · CPC title

• H10D10/40 Primary

  Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)} · CPC title

• H01L29/732

  Electricity · mapped topic

• H01L29/1004

  Electricity · mapped topic