SMD, IPD, and/or wire mount in a package

Patent metadata

Field	Value
Publication number	US-9754928-B2
Application number	US-201514737210-A
Country	US
Kind code	B2
Filing date	Jun 11, 2015
Priority date	Jul 17, 2014
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Various package structures and methods of forming package structures are described. According an embodiment, a structure includes a first package and a package component attached to the first package by external connectors. The first package comprises a device attached to a first pad and a second pad. The device is a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof. The device is attached to the first pad and the second pad through a dielectric layer. A spacer material is disposed laterally between the first pad and the second pad and is disposed between the device and the dielectric layer. An encapsulant surrounds the device and the spacer material.

First claim

What is claimed is:

1. A structure comprising:
a first package comprising a device attached to a first pad and a second pad, the device being a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof, the device being attached to the first pad and the second pad through a dielectric layer, a first spacer material being disposed directly between the first pad and the second pad and disposed between the device and the dielectric layer, an encapsulant surrounding the device and the first spacer material, wherein a sidewall of the first spacer material facing the first pad is a point of the first spacer material that is located furthest from a center of the first spacer material in a cross-sectional view, wherein the first spacer material is separated from both the first pad and the second pad by the dielectric layer; and
a package component attached to the first package by external connectors.

2. The structure of claim 1 , wherein the package component is a substrate, the external connectors being attached through the dielectric layer to respective under-metals, the encapsulant being an underfill material that further surrounds the external connectors.

3. The structure of claim 2 further comprising a second spacer material disposed between the device and the substrate, the encapsulant further surrounding the second spacer material.

4. The structure of claim 1 , wherein the package component is a second package, the external connectors being attached through the dielectric layer to respective connector pads, the encapsulant being an underfill material that further surrounds the external connectors.

5. The structure of claim 4 further comprising a second spacer material disposed between the device and the second package, the encapsulant further surrounding the second spacer material.

6. The structure of claim 1 , wherein the encapsulant further surrounds an integrated circuit die, the dielectric layer being in a redistribution structure, the redistribution structure being on the encapsulant and disposed between the encapsulant and the package component.

7. The structure of claim 1 , wherein a composition of the encapsulant is different from a composition of the first spacer material.

8. The structure of claim 1 , wherein the dielectric layer has a recess between the first pad and the second pad, the first spacer material being at least partially disposed in the recess.

9. The structure of claim 1 , wherein no air gap is between the device and the dielectric layer.

10. A structure comprising:
a first package comprising:
an integrated circuit die at least laterally encapsulated with a first encapsulant, wherein the encapsulant comprises a first material throughout the encapsulant and the first material is planar with a connector connected to the integrated circuit die;
a redistribution structure on the integrated circuit die and the first encapsulant, the redistribution structure comprising a first pad, a second pad, and a dielectric layer; and
a device attached through the dielectric layer to the first pad and the second pad, the device being a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof, a recess being in the dielectric layer between the first pad and the second pad, wherein the first pad and the second pad have a dimension in a plane parallel to a major surface of the dielectric layer and in a first direction perpendicular to a second direction, the second direction being from the first pad to the second pad, the recess having a length in the plane and in the first direction, the length being greater than the dimension.

11. The structure of claim 10 , wherein a spacer material is disposed in the recess and between the dielectric layer and the device.

12. The structure of claim 10 further comprising a package component attached to the first package using external connectors, the external connectors being mechanically coupled through the dielectric layer to conductive features in the redistribution structure, an underfill material being disposed between the package component and the first package and around the device, the underfill material being disposed in the recess and between the dielectric layer and the device.

13. The structure of claim 10 , wherein the encapsulant is disposed in the recess and between the dielectric layer and the device.

14. A structure comprising:
openings through a dielectric layer, wherein the openings expose a first pad and a second pad, the dielectric layer being in a redistribution structure in a first package;
a first spacer material on the dielectric layer between the first pad and the second pad, wherein the first spacer material does not extend beyond the first pad and the second pad in a first direction parallel with a top surface of the first pad, wherein the first spacer material is located within a recess, the recess being within the dielectric layer separate from the openings; and
a device attached to the first pad and the second pad, the device being a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof, the first spacer material being disposed between the device and the dielectric layer.

15. The structure of claim 14 , further comprising a recess within the dielectric layer between the first pad and the second pad, the first spacer material being disposed in the recess.

16. The structure of claim 14 , further comprising:
a second spacer material on a package component; and
external connectors mechanically coupled through the dielectric layer to conductive features in the redistribution structure, the second spacer material being disposed between the device and the package component.

17. The structure of claim 14 , further comprising:
external connectors connecting the first package to a substrate, the external connectors being mechanically coupled to the redistribution structure; and
an underfill material between the first package and the substrate, the underfill material encapsulating the device and the external connectors.

18. The structure of claim 14 , further comprising:
external connectors attaching the first package to a second package, the external connectors being mechanically coupled to the redistribution structure; and
an underfill material between the first package and the second package, the underfill material encapsulating the device and the external connectors.

19. The structure of claim 14 , further comprising:
an integrated circuit die adhered to the redistribution structure; and
an encapsulant encapsulating the device and the integrated circuit die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei
• Chiu Ming-Yen

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title