Semiconductor device

Patent metadata

Field	Value
Publication number	US-9754863-B2
Application number	US-201615177827-A
Country	US
Kind code	B2
Filing date	Jun 9, 2016
Priority date	Jun 12, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

The semiconductor device improves heat dissipation by loading a diode and a MOSFET or IGBT in a single package. A drain electrode disposed on a rear surface of a MOSFET chip is soldered to an upper surface of a first lead frame, and a cathode electrode disposed on a rear surface of a diode chip is soldered to an upper surface of a second lead frame. Rear surfaces of the first lead frame and second lead frame to which neither the diode chip nor the MOSFET chip is connected are disposed so as to be exposed from a sealing resin.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first lead frame; and
a second lead frame,
wherein the first lead frame has a first terminal,
a second lead frame has a second terminal,
one of principal surfaces of the first lead frame has a first semiconductor chip,
one of principal surfaces of the second lead frame has a second semiconductor chip,
a first electrode disposed on a front surface of the first semiconductor chip is electrically connected to the principal surface of the second lead frame by a bonding wire,
a front surface of the second semiconductor chip has a second electrode and a third electrode,
the second electrode is electrically connected to a third terminal and a fourth terminal by bonding wires,
the third electrode is electrically connected to a fifth terminal by a bonding wire, and
another of the principal surfaces of the first lead frame and another of the principal surfaces of the second lead frame are disposed so as to be exposed from a sealing resin.

2. The semiconductor device according to claim 1 , wherein
the first electrode is connected to one of principal surfaces of a third lead frame by a bonding wire,
the principal surface of the third lead frame is connected to the principal surface of the second lead frame by a bonding wire, and
another of the principal surfaces of the third lead frame is exposed from the sealing resin.

3. The semiconductor device according to claim 1 , wherein the first terminal, the second terminal, the third terminal, the fourth terminal, and the fifth terminal are disposed so as to be exposed from the sealing resin.

4. The semiconductor device according to claim 1 , wherein a through-hole is provided between the first lead frame and the second lead frame.

5. A semiconductor device, comprising:
a first lead frame; and
a second lead frame,
wherein the first lead frame has a first terminal,
a second lead frame has a second terminal,
one of principal surfaces of the fourth lead frame has a first semiconductor chip,
one of principal surfaces of the second lead frame has a second semiconductor chip and a third semiconductor chip,
a first electrode disposed on a front surface of the first semiconductor chip is electrically connected to the principal surface of the second lead frame by a bonding wire,
a front surface of the first semiconductor chip has a second electrode and a third electrode,
a front surface of the second semiconductor chip has a fourth electrode,
the second electrode is electrically connected a third terminal and a fourth terminal by bonding wires,
the second electrode is electrically connected to a fifth terminal by a bonding wire,
the fourth electrode is electrically connected to the second electrode by a bonding wire, and
another of the principal surfaces of the second lead frame and another of the principal surfaces of the second lead frame are disposed so as to be exposed from a sealing resin.

6. The semiconductor device according to claim 5 , wherein
the first electrode is connected to one of principal surfaces of a third lead frame by a bonding wire,
the principal surface of the third lead frame is connected to the principal surface of the second lead frame by a bonding wire, and
another of the principal surfaces of the third lead frame is exposed from the sealing resin.

7. The semiconductor device according to claim 5 , wherein the first terminal, the second terminal, the third terminal, the fourth terminal, and the fifth terminal are disposed so as to be exposed from the sealing resin.

8. A semiconductor device, comprising:
a first lead frame; and
a second lead frame,
wherein the second lead frame has a first terminal,
one of principal surfaces of the first lead frame has a first semiconductor chip,
one of principal surfaces of the second lead frame has a second semiconductor chip,
a first electrode disposed on a front surface of the first semiconductor chip is electrically connected to the principal surface of the second lead frame by a bonding wire,
a front surface of the second semiconductor chip has a second electrode and a third electrode,
the second electrode is electrically connected to a second terminal and a third terminal by bonding wires,
the third electrode is electrically connected to a fourth terminal by a bonding wire, and
another of the principal surfaces of the first lead frame and another of the principal surfaces of the second lead frame are disposed so as to be exposed from a sealing resin.

9. The semiconductor device according to claim 8 , wherein
the first electrode is connected to one of principal surfaces of a third lead frame by a bonding wire,
the principal surface of the third lead frame is connected to the principal surface of the second lead frame by a bonding wire, and
another of the principal surfaces of the third lead frame is exposed from the sealing resin.

10. The semiconductor device according to claim 8 , wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are disposed so as to be exposed from the sealing resin.

11. The semiconductor device according to claim 8 , wherein another of the principal surfaces of the first lead frame is electrically connected to a wiring pattern disposed on a substrate.

12. A semiconductor device, comprising:
a first lead frame; and
a second lead frame,
wherein the second lead frame has a first terminal,
one of principal surfaces of the first lead frame has a first semiconductor chip,
one of principal surfaces of the second lead frame has a second semiconductor chip and a third semiconductor chip,
a first electrode disposed on a front surface of the first semiconductor chip is electrically connected to the principal surface of the second lead frame by a bonding wire,
a front surface of the second semiconductor chip has a second electrode and a third electrode,
a front surface of the third semiconductor chip has a fourth electrode,
the second electrode is electrically connected to a second terminal and a third terminal by bonding wires,
the third electrode is electrically connected to a fourth terminal by a bonding wire,
the fourth electrode is electrically connected to the second electrode by a bonding wire, and
another of the principal surfaces of the second lead frame and another of the principal surfaces of the first lead frame are disposed so as to be exposed from a sealing resin.

13. The semiconductor device according to claim 12 , wherein
the first electrode is connected to one of principal surfaces of a third lead frame by a bonding wire,
the principal surface of the third lead frame is connected to the principal surface of the second lead frame by a bonding wire, and
another of the principal surfaces of the third lead frame is exposed from the sealing resin.

14. The semiconductor device according to claim 12 , wherein
the first terminal, the second terminal, the third terminal, and the fourth terminal are disposed so as to be exposed from the sealing resin.

15. The semiconductor device according to claim 12 , wherein another of the principal surfaces of the first lead frame is electrically connected to a wiring pattern disposed on a substrate.

16. A semiconductor device, comprising:
a first lead frame; and
a second lead frame,
wherein the second lead frame has a first terminal,
one of principal surfaces of the first lead frame has a first semiconductor chip,
one of principal surfaces of the second lead frame has a second semiconductor chip,
a first electrode disposed on a front surface of the se

Assignees

• Fuji Electric Co Ltd

Inventors

• Watanabe Sota
• Furihata Hiroaki
• Imai Makoto

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/50

  Bond wires · CPC title