Semiconductor transistor device and fabrication method thereof

US9754828B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9754828-B1
Application numberUS-201615200000-A
CountryUS
Kind codeB1
Filing dateJul 1, 2016
Priority dateJun 13, 2016
Publication dateSep 5, 2017
Grant dateSep 5, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor transistor device, comprising: a semiconductor substrate having an active area and a trench isolation region surrounding the active area; a gate oxide layer disposed on the active area; a gate disposed on the gate oxide layer; a spacer disposed on a sidewall of the gate; a source doping region disposed in the active area on one side of the gate; a drain doping region disposed in the active area on the other side of the gate; an insulating cap layer covering the gate, the spacer, the source doping region and the drain doping region; a redistributed contact layer (RCL) on the insulating cap layer, wherein the RCL is in direct contact with at least one of the gate, the source doping region and the drain doping region, and extends from the active area to the trench isolation region; and a contact plug directly disposed on the RCL vertically above the trench isolation region and is electrically connected to at least one of the gate, the source doping region and the drain doping region through the RCL. 2. The semiconductor transistor device according to claim 1 , wherein the insulating cap layer is in direct contact with the spacer. 3. The semiconductor transistor device according to claim 2 , wherein the insulating cap layer comprises SiOx, SiN or SiON. 4. The semiconductor transistor device according to claim 1 , wherein the RCL comprises metal or metal silicide. 5. The semiconductor transistor device according to claim 1 , wherein the RCL comprises Ti, TiN, W, SiNix, SiCox, SiTix or SiWx. 6. The semiconductor transistor device according to claim 1 , wherein the insulating cap layer comprises an opening disposed on the gate, the source doping region, or the drain doping region, wherein the RCL fills into the opening. 7. The semiconductor transistor device according to claim 1 further comprising a contact etch stop layer (CESL) covering the RCL and the insulating cap layer. 8. The semiconductor transistor device according to claim 7 , wherein the CESL comprises silicon nitride. 9. The semiconductor transistor device according to claim 7 further comprising an inter-layer dielectric (ILD) layer covering the CESL. 10. The semiconductor transistor device according to claim 9 , wherein the contact plug penetrates through the ILD layer and the CESL and is electrically connected to the RCL. 11. The semiconductor transistor device according to claim 1 , wherein the RCL electrically connects the gate with one of the source doping region and the drain doping region. 12. The semiconductor transistor device according to claim 1 , wherein the RCL traverses another gate.

Assignees

Inventors

Classifications

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

  • Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

  • Interconnections or connectors in packages · CPC title

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Frequently asked questions

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What does patent US9754828B1 cover?
A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL ex…
Who is the assignee on this patent?
United Microelectronics Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/0698. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).