Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9754826-B2
Application number	US-201615155478-A
Country	US
Kind code	B2
Filing date	May 16, 2016
Priority date	Nov 30, 2011
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a trench on an insulating interlayer on a substrate;
forming a first seed layer on an inner wall of the trench and on the insulating interlayer, the first seed layer having a first thickness on an upper portion of the trench greater than a second thickness on a lower portion of the trench;
forming a preliminary metal layer filling the lower portion of the trench by performing a reflow process on the first seed layer;
forming a wetting improvement layer on a portion of the preliminary metal layer on the upper portion of the trench; and
forming a metal layer filling the trench by an electrolytic plating process.

2. The method of claim 1 , wherein the forming a metal layer includes performing the electrolytic plating process using an additive and an electrolyte, the additive having a suppressor, an accelerator and a leveler, and the electrolyte including a copper ion, and
wherein the forming a wetting improvement layer includes forming at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

3. The method of claim 1 , further comprising:
forming a barrier layer on the inner wall of the trench and on the insulating interlayer prior to the forming a first seed layer.

4. The method of claim 1 , wherein the forming a first seed layer includes performing a sputtering process using copper as a target when a bias power is applied to the substrate.

5. The method of claim 1 , wherein the forming a preliminary metal layer exposes a portion of the inner wall of the trench, the method further comprising:
forming a second seed layer on the exposed portion of the inner wall of the trench.

6. The method of claim 4 , wherein the forming a wetting improvement layer forms the wetting improvement layer on the preliminary metal layer in the trench.

7. The method of claim 1 , further comprising:
reducing oxidized portions of the preliminary metal layer and the wetting improvement layer prior to the forming a metal layer.

8. The method of claim 1 , further comprising:
planarizing the metal layer until the insulating interlayer is exposed after the forming a metal layer,
wherein the wetting improvement layer on the upper portion of the trench is removed by the planarization of the metal layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Jong-Won
• Kim Hei-Seung
• Nam Kyoung-Hee
• Park In-Sun
• Lee Jong-Myeong

Classifications

• H10P14/47 Primary

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/0425

  comprising multiple stacked seed or nucleation layers · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/059

  by reflowing or applying pressure · CPC title