Interconnect structure and method

Patent metadata

Field	Value
Publication number	US-9754822-B1
Application number	US-201615058864-A
Country	US
Kind code	B1
Filing date	Mar 2, 2016
Priority date	Mar 2, 2016
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

First claim

What is claimed is:

1. A method comprising:
depositing a first dielectric layer over a substrate;
forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a hardness that is greater than the first dielectric layer and a K-value that is greater than the first dielectric layer;
depositing a third dielectric layer over the second dielectric layer, the third dielectric layer having a hardness that is less than the second dielectric layer and a K-value that is less than the second dielectric layer;
etching the third dielectric layer, the second dielectric layer, and the first dielectric layer to form a first opening exposing a first region over the substrate, the first opening having a via opening of a first width and a trench opening of a second width, the trench opening overlapping the via opening, the second width being greater than the first width, wherein a bottom surface of the trench opening is in the first dielectric layer or in the third dielectric layer with a first portion of the third dielectric layer disposed between the bottom surface of the trench opening and a surface of the second dielectric layer; and
filling the first opening with a conductive material to form a first conductive interconnect contacting the first region over the substrate, the first conductive interconnect comprising a via portion in the via opening and a trench portion in the trench opening.

2. The method of claim 1 , wherein the first region over the substrate comprises a conductive element, the first conductive interconnect contacting the conductive element.

3. The method of claim 1 , wherein the second dielectric layer contacts the via portion of the first conductive interconnect.

4. The method of claim 1 , wherein the second dielectric layer contacts the trench portion of the first conductive interconnect.

5. The method of claim 1 , wherein forming the second dielectric layer on the first dielectric layer comprises:
performing a plasma treatment process on the first dielectric layer to form the second dielectric layer on the first dielectric layer, wherein after the plasma treatment process, the first dielectric layer has a thickness less than a thickness of the first dielectric layer before the plasma treatment process.

6. The method of claim 1 , wherein forming the second dielectric layer on the first dielectric layer comprises:
depositing the second dielectric layer on the first dielectric layer.

7. The method of claim 1 , wherein filling the first opening with the conductive material comprises:
lining the first opening with a barrier layer;
filling the lined first opening with the conductive material; and
planarizing the conductive material, barrier layer, and third dielectric layer to remove excess conductive material and barrier layer over a top surface of the third dielectric layer to form the first conductive interconnect contacting the first region over the substrate.

8. The method of claim 1 further comprising:
depositing an etch stop layer over the substrate, the first dielectric layer being formed over and contacting the etch stop layer, the first opening extending through the etch stop layer.

9. The method of claim 1 , wherein the first dielectric layer has a K-value of 2.6 or less and the second dielectric layer has a K-value of 2.8 or greater.

10. A method comprising:
depositing a first dielectric layer having a first thickness over a conductive element over a substrate;
performing a plasma treatment process to convert a top portion of the first dielectric layer into an insert layer, the insert layer having a K-value that is greater than the first dielectric layer, wherein after the plasma treatment process, a remaining lower portion of the first dielectric layer has a second thickness less than the first thickness;
depositing a second dielectric layer over the insert layer, the second dielectric layer having a K-value that is less than the insert layer;
etching the second dielectric layer, the insert layer, and the first dielectric layer to form a via opening exposing the conductive element over the substrate; and
etching the second dielectric layer to form a trench opening overlapping the via opening, the trench opening having a greater width than the via opening, a first portion of the second dielectric layer being interposed between a bottom surface of the trench opening and a top surface of the insert layer.

11. The method of claim 10 , wherein the first dielectric layer has a K-value of 2.6 or less and the insert layer has a K-value of 2.8 or greater.

12. The method of claim 10 further comprising:
filling the via opening and the trench opening with a conductive material to form a first conductive interconnect contacting the conductive element on the substrate, the first conductive interconnect comprising a via portion in the via opening and a trench portion in the trench opening.

13. The method of claim 12 , wherein the insert layer contacts the via portion of the first conductive interconnect.

14. The method of claim 10 further comprising:
depositing an etch stop layer over the substrate and the conductive element within the substrate, the first dielectric layer being formed over and contacting the etch stop layer, the via opening extending through the etch stop layer.

15. The method of claim 10 , wherein the conductive element is a conductive contact, the conductive contact electrically contacting a source/drain region of a fin field-effect transistor (FinFET).

16. A method comprising:
forming a fin extending from a substrate;
forming an isolation regions surrounding the fin;
forming a gate structure on a top surface and sidewalls of the fin;
forming a source region and a drain region on the fin, the gate structure being interposed between the source region and the drain region;
forming an interlayer dielectric over the fin, the source region, the drain region, the isolation region, and the gate structure;
forming a conductive contact extending through the interlayer dielectric to contact the source region or the drain region;
depositing a first dielectric layer over interlayer dielectric and the conductive contact;
forming an insert layer over and in contact with the first dielectric layer, the insert layer having a hardness that is greater than the first dielectric layer and a K-value that is greater than the first dielectric layer;
depositing a second dielectric layer over and in contact with the insert layer, the second dielectric layer having a hardness that is less than the insert layer and a K-value that is less than the insert layer; and
forming a first conductive interconnect extending through the second dielectric layer, the insert layer, and the first dielectric layer to contact the conductive contact, the first conductive interconnect comprising a via of a first width and a trench of a second width, the trench overlapping the via, the second width being greater than the first width, wherein a bottom surface of the trench is in the first dielectric layer, or is separated from a surface of the insert layer by a first portion of the second dielectric layer.

17. The method of claim 16 , wherein the insert layer contacts the via of the first conductive interconnect.

18. The method of claim 16 , wherein the insert layer contacts the trench of the first conductive interconnect.

19. The method of claim 16 , wherein forming the insert layer on the first dielectric layer comprises:
performing a plasma treatment process on the first dielectric laye

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Chia-Cheng
• Chi Chih-Chien
• Ko Chung-Chi
• Chang Yao-Jen
• Kao Chen-Yuan
• Kuo Kai-Shiang
• Shih Po-Cheng
• Lee Tze-Liang
• Ruan jun-yi

Classifications

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title