Method of fabricating semiconductor device and computing system for implementing the method

Patent metadata

Field	Value
Publication number	US-9754789-B2
Application number	US-201414509316-A
Country	US
Kind code	B2
Filing date	Oct 8, 2014
Priority date	Oct 21, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a target layer;
forming a first mask on the target layer to expose a first region;
subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction;
subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction; and
etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.

2. The method of claim 1 , wherein the target layer comprises an oxide layer.

3. The method of claim 1 , wherein the forming of the first mask comprises:
sequentially forming a first organic layer, an oxide layer, and a hard mask layer on the target layer; and
patterning the hard mask layer using the oxide layer as an etch-stop layer.

4. The method of claim 3 , wherein the oxide layer comprises a same material as the target layer.

5. The method of claim 3 , wherein the patterning of the hard mask layer comprises:
sequentially forming a second organic layer and a photoresist pattern on the hard mask layer; and
etching, using the photoresist pattern, the second organic layer and the hard mask layer until the oxide layer is exposed.

6. The method of claim 3 , wherein the forming a third mask comprises:
forming a second organic layer and a photoresist pattern on the oxide layer; and
patterning the second organic layer using the photoresist pattern as a mask and using the oxide layer as an etch-stop layer.

7. The method of claim 6 , wherein the etching the target layer such that the first and second sub regions are defined in the target layer comprises:
exposing the target layer by etching the oxide layer and the first organic layer using the first and third masks; and
etching the exposed target layer and the oxide layer together.

8. The method of claim 7 , further comprising:
ashing the first organic layer.

9. The method of claim 1 , further comprising:
forming a conductive layer to contact an active pattern underlying the target layer in the first and second sub regions and the second region.

10. The method of claim 9 , wherein the active pattern comprises an active fin extending along the first direction, and the forming a target layer further comprises forming a gate electrode on the active fin to extend along the second direction.

11. The method of claim 1 , further comprising:
forming a conductive layer in the first and second sub regions and the second region, and
wherein the forming a target layer includes,
forming an active pattern;
forming a silicide contact on the active pattern to contact the conductive layer; and
forming the target layer on the silicide contact.

12. A method of fabricating a semiconductor device, the method comprising:
receiving a layout design in which first and second patterns formed using double patterning lithography are defined, the first pattern including a first sub pattern and a second sub pattern separated from the first sub pattern by a first gap;
generating a first mask for exposing regions defined as the first and second sub patterns and a region between the first and second sub patterns;
generating a second mask for exposing a region defined as the second pattern; and
generating a third mask for dividing a region exposed by the first mask into the regions defined as the first and second sub patterns,
wherein in the layout design, a region defined as the first pattern and the region defined as the second pattern are separated from each other in a first direction, and the region defined as the first sub pattern and the region defined as the second sub pattern are separated from each other in a second direction intersecting the first direction.

13. The method of claim 12 , wherein a first active contact pattern is formed on an active pattern in the region defined as the first pattern, and a second active contact pattern is formed on the active pattern in the region defined as the second pattern.

14. The method of claim 12 , wherein the second pattern comprises a third sub pattern and a fourth sub pattern separated from the third sub pattern by a second gap greater than the first gap.

15. The method of claim 14 , wherein the first gap is equal to or smaller than a critical dimension of the double patterning lithography, and the second gap is greater than the critical value.

16. A method of forming patterns separated by a gap smaller than a critical dimension, the method comprising:
forming a target layer;
forming an insulating layer over the target layer;
forming a first mask on the insulating layer to expose a first region extending in a first direction;
forming a second mask to cover a second region, the second region being a region separating the first region into two sub-regions in a second direction intersecting the first direction;
etching, using the first and second masks, the target layer to form two openings therein such that the two openings are separated by a gap corresponding to the second region, extend in the first direction, and expose underlying conductive members therethrough; and
forming conductive patterns confined by the two openings such that the conductive patterns physically contact the underlying conductive members.

17. The method of claim 16 , wherein the forming an insulating layer comprises:
sequentially forming a first organic layer, an oxide layer, and a first hard mask layer on the target layer.

18. The method of claim 17 , wherein the forming a first mask comprises:
sequentially forming a second organic layer and a first photoresist pattern on the first hard mask layer; and
etching the second organic layer and the first hard mask layer until the oxide layer is exposed.

19. The method of claim 18 , wherein the forming a second mask comprises:
selectively removing the first hard mask layer in the first region;
sequentially forming a third organic layer and a second photoresist pattern on the oxide layer; and
patterning the second organic layer using the second photoresist pattern as a mask and using the oxide layer as an etch-stop layer.

Assignees

• Kim Yoon-Hae
• Yoon Jong-Shik
• Rhee Hwa-Sung
• Kim Byung-Sung
• Samsung Electronics Co Ltd

Inventors

• Kim Yoon-Hae
• Yoon Jong-Shik
• Rhee Hwa-Sung
• Kim Byung-Sung

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10P14/40 Primary

  of conductive or resistive materials · CPC title