Methods of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-9754785-B2
Application number	US-201614993141-A
Country	US
Kind code	B2
Filing date	Jan 12, 2016
Priority date	Jan 14, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

In a method of manufacturing a semiconductor device, sacrificial layer patterns extending in a first direction are formed on an etch target layer. Preliminary mask patterns are formed on opposite sidewall surfaces of each of the sacrificial layer patterns. A filling layer is formed to fill a space between the preliminary mask patterns. Upper portions of the preliminary mask patterns are etched to form a plurality of mask patterns. Each of the mask patterns is symmetric with respect to a plane passing a center point of each of the mask patterns in a second direction substantially perpendicular to the first direction and extending in the first direction. The sacrificial layer patterns and the filling layer are removed. The etch target layer is etched using the mask patterns as an etching mask to form a plurality of target layer patterns.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of sacrificial layer line patterns on an etch target, each of the sacrificial layer line patterns extending longitudinally in a first direction so as to have sidewall surfaces facing in a second direction substantially perpendicular to the first direction;
forming preliminary mask patterns on the sidewall surfaces of the sacrificial layer patterns, respectively;
forming a filling layer in spaces between the preliminary mask patterns;
etching back the preliminary mask patterns to remove upper portions of the preliminary mask patterns to form a plurality of while leaving lower portions of the preliminary mask patterns on the sidewall surfaces of the sacrificial layer patterns as a plurality of finalized mask patterns, respectively, each of the finalized mask patterns being symmetric with respect to a plane passing a center point of each of the finalized mask patterns in the second direction and extending in the first direction;
removing the sacrificial layer line patterns and the filling layer while substantially leaving the plurality of finalized mask patterns on the etch target;
etching the etch target using by performing an etch process in which the plurality of finalized mask patterns as constitutes an etching mask to form a plurality of target layer patterns; and
forming an upper mask having respective sections disposed on the sacrificial layer patterns, respectively,
wherein the sections of the upper mask are left on the sacrificial layer patterns during the forming of the preliminary mask patterns, and the etching back of the preliminary mask patterns removes the sections of the upper mask as the upper portions of the preliminary mask patterns are being removed.

2. The method of claim 1 , wherein the sacrificial layer line patterns and the filling layer are formed of substantially the same materials.

3. The method of claim 2 , wherein the sacrificial layer line patterns and the filling layer together constitute a carbon-containing layer or a polysilicon layer.

4. The method of claim 1 , wherein forming the preliminary mask patterns includes:
conformally forming a mask layer on the sacrificial layer patterns and the etch target; and
anisotropically etching the mask layer.

5. The method of claim 1 , wherein each of the sacrificial layer line patterns has a width substantially equal to a first distance, and a distance between adjacent ones of the sacrificial layer line patterns is substantially the same as the sum of the first distance and twice a first width, the first distance being substantially equal to a distance between adjacent ones of the target layer patterns, and the first width being substantially equal to the width of each of the target layer patterns.

6. The method of claim 5 , wherein each of the preliminary mask patterns is formed to have the first width.

7. The method of claim 1 , wherein each of the sacrificial layer line patterns has a width greater than a first distance, and a distance between adjacent ones of the sacrificial layer patterns is less than the sum of the first distance and twice a first width, the first distance being substantially equal to a distance between adjacent ones of the target layer patterns, and the first width being substantially equal to the width of each of the target layer patterns.

8. The method of claim 7 , wherein each of the preliminary mask patterns is formed to have a width less than the first width.

9. The method of claim 8 , wherein a distance between the preliminary mask patterns is greater than the first distance.

10. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of sacrificial layer line patterns on an etch target, each of the sacrificial layer patterns extending longitudinally in a first direction;
conformally forming a mask layer on the sacrificial layer pattern and the etch target;
forming a filling layer in spaces between neighboring portions of the mask layer;
etching upper portions of the mask layer to expose a top surface of the sacrificial layer pattern to form a plurality of mask patterns, each of the mask patterns including a first linear section, a second linear section and a connecting portion connecting the first and second linear sections to each other at bottom parts of the first and second linear portions;
removing the sacrificial layer line patterns and the filling layer; and
anisotropically etching the connecting portion of each of the mask patterns and the etch target to form a plurality of target layer patterns.

11. The method of claim 10 , further comprising forming an upper mask having sections disposed on the sacrificial layer patterns, respectively.

12. The method of claim 11 , wherein the upper mask pattern is removed when the upper portions of the preliminary mask patterns are etched.

13. The method of claim 10 , further comprising forming a lower mask layer on the etch target.

14. A method of manufacturing a semiconductor device, comprising:
forming a sacrificial layer pattern structure on an etch target;
selectively etching the sacrificial layer pattern structure to form holes extending therethrough and exposing the etch target; and
subsequently etching the etch target using the sacrificial layer pattern structure as an etch mask to thereby form holes in the etch target corresponding to the holes extending through the sacrificial layer pattern structure,
wherein the forming of the sacrificial layer pattern structure comprises:
forming a first sacrificial layer on the etch target,
forming a first mask layer on the sacrificial layer,
forming a plurality of sacrificial layer line patterns on the first mask layer, each of the sacrificial layer line patterns extending longitudinally in a first direction so as to have sidewall surfaces facing in a second direction substantially perpendicular to the first direction,
forming preliminary mask patterns on the sidewall surfaces of the sacrificial layer patterns, respectively,
forming a filling layer in spaces between the preliminary mask patterns,
etching upper portions of the preliminary mask patterns to form a plurality of first mask patterns, each of the first mask patterns being symmetric with respect to a plane passing a center point of each of the mask patterns in the second direction and extending in the first direction,
removing the sacrificial layer line patterns and the filling layer, and
etching the first mask layer using the first mask patterns as an etch mask to form a first mask having sections extending longitudinally in the first direction and spaced apart in the second direction, and etching the first sacrificial layer using the first mask to form first sacrificial layer patterns extending longitudinally in the first direction.

15. The method of claim 14 , wherein the sacrificial layer line patterns and the filling layer are formed of substantially the same materials.

16. The method of claim 14 , wherein forming the preliminary mask patterns includes:
conformally forming a mask layer on the sacrificial layer patterns and the etch target; and
anisotropically etching the mask layer conformally formed on the sacrificial layer patterns and the etch target.

17. The method of claim 14 , wherein the etching of the sacrificial layer pattern structure comprises forming a second mask on the sacrificial layer pattern structure, and etching the sacrificial layer pattern structure using the second mask as an etch mask, and
the forming of the second mas

Assignees

• Kim Eun-Jung
• Kwon Sung-Un
• Kim Yong-Kwan
• Hwang Yoo-Sang
• Seo Young-Sik
• Samsung Electronics Co Ltd

Inventors

• Kim Eun-Jung
• Kwon Sung-Un
• Kim Yong-Kwan
• Hwang Yoo-Sang
• Seo Young-Sik

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H01L21/31144

  Electricity · mapped topic