Sensing circuit and method utilizing voltage replication for non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9754640-B1
Application number	US-201615297199-A
Country	US
Kind code	B1
Filing date	Oct 19, 2016
Priority date	Oct 19, 2016
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A sensing circuit for a non-volatile memory device is provided. The sensing circuit includes a bias generating circuit and a first sense amplifier. The bias generating circuit includes a driving circuit biased by a reference current and an operational amplifier. The operation amplifier receives a reference voltage at a non-inverting input terminal, and generates an output voltage at an inverting input terminal via a negative feedback path including the driving circuit. The first sense amplifier includes a first replica circuit and a first current sensing circuit. The first replica circuit replicates the output voltage to a first bit line coupled to a first memory cell. The first current sensing circuit senses a first current difference between a scaled version of the reference current and a first cell current of the first memory cell to determine a first memory state of the first memory cell.

First claim

What is claimed is:

1. A sensing circuit for a non-volatile memory device, comprising:
a bias generating circuit, comprising:
a driving circuit, biased by a reference current; and
an operational amplifier, for receiving a reference voltage at a non-inverting input terminal of the operational amplifier, and generating an output voltage at an inverting input terminal of the operational amplifier via a negative feedback path comprising the driving circuit; and
a first sense amplifier, comprising:
a first replica circuit, coupled to the bias generating circuit, for replicating the output voltage to a first bit line coupled to a first memory cell; and
a first current sensing circuit, coupled to the first replica circuit, for sensing a first current difference between a scaled version of the reference current and a first cell current of the first memory cell to determine a first memory state of the first memory cell.

2. The sensing circuit according to claim 1 , further comprising:
a second sense amplifier, comprising:
a second replica circuit, coupled to the bias generating circuit, for replicating the output voltage to a second bit line coupled to a second memory cell; and
a second current sensing circuit, coupled to the second replica circuit, for sensing a second current difference between a scaled version of the reference current and a second cell current of the second memory cell to determine a second memory state of the second memory cell.

3. The sensing circuit according to claim 1 , wherein the first replica circuit comprises a first current mirror configured to mirror the reference current.

4. The sensing circuit according to claim 1 , wherein the first current sensing circuit comprises:
a sensing transistor, configured to detect the first cell current;
a sensing current mirror, configured to mirror a current flowing through the sensing transistor;
a scaled reference current mirror, configured to mirror the scaled version of the reference current; and
a current comparator, configured to compare a current of the sensing current mirror and a current of the scaled reference current mirror to determine the first memory state of the first memory cell.

5. The sensing circuit according to claim 1 , wherein the driving circuit comprises:
a first PMOS transistor, having a source, a drain, and a gate coupled to the drain to provide a first bias voltage; and
a first NMOS transistor, having a source coupled to the inverting input terminal of the operational amplifier, a drain coupled to the drain of the first PMOS transistor, and a gate coupled to an output terminal of the operational amplifier to provide a second bias voltage.

6. The sensing circuit according to claim 5 , wherein the first replica circuit comprises:
a second PMOS transistor, having a source, a drain, and a gate coupled to the first bias voltage; and
a second NMOS transistor, having a source coupled to the first bit line, a drain coupled to the drain of the second PMOS transistor, and a gate coupled to the second bias voltage.

7. The sensing circuit according to claim 6 , wherein the first PMOS transistor and the second PMOS transistor are equal in size, and the first NMOS transistor and the second NMOS transistor are equal in size.

8. The sensing circuit according to claim 6 , wherein the first current sensing circuit comprises:
a third NMOS transistor, having a source, a drain coupled to the first bit line, and a gate coupled to the drain of the second NMOS transistor;
a third PMOS transistor, having a source, a drain, and a gate coupled to the first bias voltage;
a fourth NMOS transistor, having a source, a drain coupled to the drain of the third PMOS transistor, and a gate coupled to the gate of the third NMOS transistor;
a fourth PMOS transistor, having a source, a drain coupled to the source of the second PMOS transistor, and a gate coupled to an enable signal; and
a fifth NMOS transistor, having a source, a drain coupled to the gate of the fourth NMOS transistor, and a gate coupled to the enable signal.

9. The sensing circuit according to claim 8 , wherein the first sense amplifier is configured to enable or disable the current sensing operation in response to the enable signal.

10. The sensing circuit according to claim 9 , wherein the reference current is two times of a current of a reference memory cell, and a size of the first PMOS transistor is two times of a size of the third PMOS transistor.

11. A sensing method for a non-volatile memory device, comprising:
biasing a driving circuit by a reference current;
receiving a reference voltage at a non-inverting input terminal of an operational amplifier;
generating an output voltage at an inverting input terminal of the operational amplifier via a negative feedback path comprising the driving circuit;
replicating the output voltage to a first bit line coupled to a first memory cell; and
sensing a first current difference between a scaled version of the reference current and a first cell current of the first memory cell to determine a first memory state of the first memory cell.

12. The sensing method according to claim 11 , further comprising:
replicating the output voltage to a second bit line coupled to a second memory cell; and
sensing a second current difference between a scaled version of the reference current and a second cell current of the second memory cell to determine a second memory state of the second memory cell.

13. The sensing method according to claim 11 , wherein the step of replicating the output voltage to the first bit line comprises:
enabling a first current mirror to mirror the reference current.

14. The sensing method according to claim 11 , wherein the step of sensing the first current difference between the scaled version of the reference current and the first cell current of the first memory cell comprises:
detecting the first cell current by a sensing transistor;
enabling a sensing current mirror to mirror a current flowing through the sensing transistor;
enabling a scaled reference current mirror to mirror the scaled version of the reference current; and
comparing a current of the sensing current mirror and a current of the scaled reference current mirror to determine the first memory state of the first memory cell.

15. The sensing method according to claim 11 , wherein the driving circuit comprises:
a first PMOS transistor, having a source, a drain, and a gate coupled to the drain to provide a first bias voltage; and
a first NMOS transistor, having a source coupled to the inverting input terminal of the operational amplifier, a drain coupled to the drain of the first PMOS transistor, and a gate coupled to an output terminal of the operational amplifier to provide a second bias voltage.

16. The sensing method according to claim 15 , wherein the step of replicating the output voltage to the first bit line is performed by a first replica circuit, comprising:
a second PMOS transistor, having a source, a drain, and a gate coupled to the first bias voltage; and
a second NMOS transistor, having a source coupled to the first bit line, a drain coupled to the drain of the second PMOS transistor, and a gate coupled to the second bias voltage.

17. The sensing method according to claim 16 , wherein the first PMOS transistor and the second PMOS transistor are equal in size, and the first NMOS transistor and the second NMOS transistor are equal in size.

18. The sensing method according to claim 16 , wherein the step of sensing the first current difference is performed

Assignees

• Macronix Int Co Ltd

Inventors

• Yang Shang-Chi

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C7/062 Primary

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title