Forward late predictive rendering in a graphics system

Patent metadata

Field	Value
Publication number	US-9754344-B2
Application number	US-201514645210-A
Country	US
Kind code	B2
Filing date	Mar 11, 2015
Priority date	Jun 27, 2014
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A graphics processing operation may include a set of render target operations, in which render targets are read and one or more intermediate computations are performed before generating final render target output. A method of performing graphics processing includes determining a dependency between render targets and defining a scheduling of tiles to reduce or eliminate a need to write intermediate computations to external memory. An interleaved order may be determined to maintain intermediate computations of dependent render target operations in an on-chip cache hierarchy.

First claim

What is claimed is:

1. In a graphics processing system, a method comprising:
determining a dependence relationship between at least two render targets (RTs) of a graphics processing operation;
performing a tile mapping of destination tiles to source tiles based on the dependence relationship and utilizing the tile mapping to determine an interleaving schedule;
determining the interleaving schedule defining an order of tile processing of the graphics processing operation to maintain intermediate tile processing results of dependent render targets of the graphics processing operation in an on-chip cache; and
rendering tiles using the interleaving schedule;
wherein performing tile mapping comprises mapping a destination tile back to source tiles.

2. The method of claim 1 , wherein determining the dependence relationship includes generating a dependence graph per set of interdependent render targets.

3. The method of claim 2 , wherein a dependency analysis module generates the dependence graph per set of the interdependent RTs.

4. The method of claim 1 , further comprising generating a mask indicating which source tiles are read to generate a destination tile.

5. The method of claim 4 , further comprising generating a use count per source tile and based on the use count determining when a source tile has been read for a final time.

6. The method of claim 1 , further comprising determining when a source tile has been read for a final tile and in response marking related cache lines for at least one of eviction and invalidation.

7. The method of claim 1 , wherein tile mapping comprises utilizing a binning unit to determine which tiles in a first RT are intersected by triangles in a second RT.

8. The method of claim 1 , wherein determining an interleaving schedule comprises determining an implication of a dependency mapping on resource usage and an order of tile processing.

9. The method of claim 1 , further comprising determining a truncation of a dependency mapping of the dependency relationship.

10. In a graphics processing system, a method comprising:
determining a dependence relationship between at least two render targets (RTs) of a graphics processing operation;
determining an interleaving schedule defining an order of tile processing of the graphics processing operation to maintain intermediate tile processing results of dependent render targets of the graphics processing operation in an on-chip cache; and
rendering tiles using the interleaving schedule;
wherein source tiles that are not required to produce the destination tile are not included in the interleaving schedule eliminating unneeded work.

11. In a graphics processing system, a method comprising:
determining a dependence relationship between at least two render targets (RTs) of a graphics processing operation;
determining an interleaving schedule defining an order of tile processing of the graphics processing operation to maintain intermediate tile processing results of dependent render targets of the graphics processing operation in an on-chip cache; and
rendering tiles using the interleaving schedule;
wherein a number of levels of the dependency mapping is limited to truncate the dependency mapping.

12. In a graphics processing system, a method comprising:
determining a dependence relationship between at least two render targets (RTs) of a graphics processing operation;
performing a tile mapping of destination tiles to source tiles based on the dependence relationship;
scheduling an interleaved order of tile processing for a sequence of render target steps having a dependency of render targets utilizing the tile mapping, the interleaved order selected to maintain a set of intermediate tile processing computations of dependent render targets in an on-chip cache of a graphics processing unit in the graphics processing system; and
rendering tiles using the interleaving order of tile processing,
wherein performing tile mapping comprises mapping a destination tile back to source tiles.

13. The method of claim 12 , wherein the interleaved order is selected to have a maximum likelihood of maintaining intermediate tile processing computations in an on-chip cache.

14. In a graphics processing system, a method comprising:
scheduling an interleaved order of tile processing for a sequence of render target steps having a dependency of render targets, the interleaved order selected to maintain a set of intermediate tile processing computations of dependent render targets in an on-chip cache of the graphics processing system; and
rendering tiles using the interleaving order of tile processing;
wherein the tile-level dependency is determined by mapping a destination tile back to source tiles to determine a dependency mapping.

15. In a graphics processing system, a method comprising:
scheduling an interleaved order of tile processing for a sequence of render target steps having a dependency of render targets, the interleaved order selected to maintain a set of intermediate tile processing computations of dependent render targets in an on-chip cache of the graphics processing system; and
rendering tiles using the interleaving order of tile processing;
wherein the interleaved order is further selected based on the dependency to omit tiles not required by the dependency to generate a final result of the sequence of render target steps.

16. A graphics system, comprising:
a graphics processing unit having an on-chip cache;
a dependency analysis module to determine dependencies in a graphics processing operation including a set of interdependent render target operations; and
a scheduling module to schedule an interleaved order of tile processing of the graphics processing operation, based on the dependency analysis, to maintain intermediate tile processing computations in the on-chip cache of the graphics processing unit,
the graphics system being configured to:
perform a tile mapping of destination tiles to source tiles based on the dependence relationship, wherein the tile mapping is utilized to determine the schedule of the interleaved order; and
render tiles using the schedule of the interleaved order,
wherein performing tile mapping comprises mapping a destination tile back to source tiles.

17. The graphics system of claim 16 , wherein the graphics processing unit comprises programmable graphics hardware and the programmable graphics hardware is programmed to assist in the dependency analysis.

18. The graphics system of claim 16 , wherein a driver performs a target dependency analysis and the driver schedules the interleaved order of tile processing.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Brothers John W
• Abraham Santosh

Classifications

• G09G5/393

  Arrangements for updating the contents of the bit-mapped memory · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G09G2350/00

  Solving problems of bandwidth in display systems · CPC title

• G06F8/433

  Dependency analysis; Data or control flow analysis · CPC title