Analog multiplier using a memristive device and method for implemening Hebbian learning rules using memrisor arrays

Patent metadata

Field	Value
Publication number	US-9754203-B2
Application number	US-201414219007-A
Country	US
Kind code	B2
Filing date	Mar 19, 2014
Priority date	Mar 24, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables.

First claim

What is claimed is:

1. An analog multiplier, comprising:
an input circuit,
a memristor, and
an output circuit;
wherein the memristor is coupled between the input circuit and the output circuit;
wherein the input circuit is arranged to:
receive or generate a first variable and a second variable;
generate at least one memristive device input signal that once provided to the memristor will cause a change in a state variable of the memristor, wherein the change in the state variable of the memristor reflects a product of the first and second variables;
provide to the memristor the at least one memristive device input signal; and

wherein the output circuit is arranged to evaluate the state variable of the memristor and to generate information about the above product.

2. The analog multiplier according to claim 1 , wherein a derivative of the state variable equals an output of a first function applied on the state variable and on the at least one memristive input signal; and
an output signal of the memristor equals a product of the at least one memristive device input signal and an output of a second function applied on the state variable and on the at least one memristive device input signal;
wherein the input circuit is arranged to generate the at least one memristive device input signal in response to the first and second functions.

3. The analog multiplier according to claim 1 , wherein the input circuit is configured to provide to the memristor the at least one memristive device input signal through a single transistor.

4. The analog multiplier according to claim 1 , wherein the input circuit is arranged to generate a memristive device input signal of a value that represents the first variable and to cause the memristor to receive the value during a duration that represents the second variable.

5. The analog multiplier according to claim 1 , wherein the at least one memristive device input signal is a voltage signal.

6. The analog multiplier according to claim 1 , wherein the at least one memristive device input signal is a current signal.

7. The analog multiplier according to claim 1 , wherein the input circuit comprises first and second transistors, the first transistor is arranged to provide positive memristive device input signals and the second transistor is arranged to provide negative memristive device input signals.

8. A device, comprising:
an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a single memristor;
an interfacing circuit that is coupled to each cell of the array of cells;
wherein the interfacing circuit is arranged to:
receive or generate first variables and second variables;
generate memristive device input signals that once provided to memristors of the array will cause a change in a state variable of each of the memristors of the array, wherein the change in the state variable of each of the memristors of the array reflects a product of one of the first variables and one of the second variables;
provide the memristive device input signals to memristors of the array; and
receive output signals that are a function of at least products of the first variables and the second variables.

9. The analog multiplier according to claim 1 wherein the output circuit is arranged to evaluate the state variable of the memristor by providing to the memristor a memristive device input signal of a first value during a first half of a read period and providing to the memristor the memristive device input signal of a second value during a second half of the read period; wherein the first value is an additive inverse of the second value.

10. The device according to claim 8 , wherein the interfacing circuit is arranged to generate memristive device input signals of values that represents the first variables and to cause the memristors to receive the values during durations that represent the second variables.

11. The device according to claim 8 , wherein the interfacing circuit is arranged to:
provide a same first memristive device input signal to all memristors of a single row of the array;
send a same second memristive device input signal to all memristors of a single column of the array; and
read in parallel states of memristors of a single column of the array.

12. The device according to claim 8 comprising an additional array of cells, wherein the cells of the additional array are arranged in columns and rows; wherein each cell of the additional array comprises a single memristor that is configured to perform a subtraction operation on a weight associated a corresponding cell of the array.

13. The device according to claim 8 , wherein the interfacing circuit is arranged to receive, from each column of cells, an aggregate current that is a sum of output currents of memristors of cells of the column.

14. The device according to claim 8 , wherein the interfacing circuit and the array of cells form an array of synapses.

15. The device according to claim 8 , comprising a machine learning controller that is arranged to execute machine learning algorithms that involve feeding to the interfacing circuit the first and second variables.

16. A method for analog multiplication of a first variable and a second variable, the method comprises:
generating or receiving the first variable and the second variable;
generating at least one memristive device input signal that once provided to a memristor will cause a change in a state variable of the memristor, wherein the change in the state variable of the memristor reflects a product of the first and second variables;
providing to the memristor the at least one memristive device input signal;
evaluating the state variable of the memristor; and
generating information about the product.

17. The method according to claim 16 , wherein a derivative of the state variable equals an output of a first function applied on the state variable and on the at least one memristive input signal; and an output signal of the memristor equals a product of the at least one memristive device input signal and an output of a second function applied on the state variable and on the at least one memristive device input signal; and
wherein the method comprises generating the at least one memristive device input signal in response to the first and second functions.

18. The method according to claim 16 , comprising providing to the memristor the at least one memristive device input signal through a single transistor.

19. The method according to claim 16 , comprising generating a memristive device input signal of a value that represents the first variable and causing the memristor to receive the value during a duration that represents the second variable.

20. The method according to claim 16 , wherein the at least one memristive device input signal is a voltage signal.

21. The method according to claim 16 , wherein the at least one memristive device input signal is a current signal.

22. The method according to claim 16 , comprising providing by a first transistor memristive device input signals and providing by a second transistor negative memristive device input signals.

23. A method, comprising:
receiving or generating first variables and second variables;
generating memristive device input signals that once provided to memristors of an array of cells will cause a change in a state variable of each of the memristors of the cells of the array, wherein the change in t

Assignees

• Technion Res & Dev Foundation

Inventors

• Di Castro Dotan
• Soudry Daniel
• Kvatinsky Shahar
• Gal Asaf
• Kolodny Avinoam

Classifications

• G06G7/163

  using a variable impedance controlled by one of the input signals, variable amplification or transfer function {(G06G7/161, G06G7/162 take precedence)} · CPC title

• G06N3/065 Primary

  Analogue means · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/0635 Primary

  Physics · mapped topic