Layout optimization for integrated circuit design

Patent metadata

Field	Value
Publication number	US-9754073-B2
Application number	US-201615237286-A
Country	US
Kind code	B2
Filing date	Aug 15, 2016
Priority date	Mar 15, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

First claim

What is claimed is:

1. A method comprising:
receiving a target pattern that is defined by a main pattern, a first cut pattern associated with a first mask, and a second cut pattern associated with a second mask, the first mask being different than the second mask;
with a computing system, checking the target pattern for compliance with a first constraint associated with the first cut pattern;
with the computing system, checking the target pattern for compliance with a second constraint associated with the second cut pattern;
with the computing system, modifying the target pattern to create a modified target pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking; and
fabricating, using the first mask and the second mask, an integrated circuit associated with the modified target pattern.

2. The method of claim 1 , wherein the first constraint is at least one of: distance between adjacent cut features and number of neighbors within a specified distance from a cut feature.

3. The method of claim 1 , wherein the first constraint and the second constraint comprise keep-out-zones defining a region surrounding a corresponding cut feature.

4. The method of claim 3 , wherein placement of a cut feature is in violation of the first constraint if a main feature has an end within the keep-out-zone associated with the cut feature.

5. The method of claim 3 , wherein placement of a cut feature is in violation of the first constraint if the keep-out-zone overlaps with a keep-out-zone associated with an adjacent cut feature.

6. The method of claim 3 , wherein a keep-out zone is in a shape of one of: a square, a rectangle, a circle, or an ellipse.

7. The method of claim 1 , wherein the modifying comprises one of: repositioning a cut feature, resizing a cut feature, reshaping a cut feature, extending an end of a main feature of the main pattern, or adding a dummy feature to the main pattern.

8. The method of claim 1 , wherein the first constraint is different than the second constraint.

9. A method comprising:
with a computing system, receiving a target pattern;
decomposing the target pattern into a main pattern and an original cut pattern, the original cut pattern comprising a plurality of cut features;
with the computing system, associating a keep-out-zone with each of the plurality of cut features;
decomposing, based on the keep-out-zones associated with each of the plurality of cut features, the original cut pattern into a first cut pattern associated with a first mask and a second cut pattern associated with a second mask; and
fabricating an integrated circuit using the first mask and the second mask, the first mask being different than the second mask.

10. The method of claim 9 , wherein the keep-out-zones define a region surrounding a corresponding cut feature.

11. The method of claim 10 , wherein the decomposing is performed so as to reduce overlap of keep-out-zones on respective cut patterns.

12. The method of claim 10 , wherein a violation of the first constraint occurs if an area of overlap of keep-out-zones from two adjacent cut features exceeds a predetermined threshold.

13. The method of claim 9 , further comprising, modifying either the main pattern, the first cut pattern, or the second cut pattern in response to determining that the decomposition cannot be done without violating either the first constraint or the second constraint.

14. The method of claim 11 , wherein the modifying comprises one of: repositioning a cut feature, resizing a cut feature, reshaping a cut feature, extending an end of a main feature of the main pattern, or adding a dummy feature to the main pattern.

15. The method of claim 9 , further comprising, decomposing the main pattern into a first main pattern and a second main pattern, wherein the first main pattern is associated with the first cut pattern and the second main pattern is associated with the second cut pattern.

16. The method of claim 15 , wherein the decomposing is such that if a cut feature covers an end of a main feature associated with the first main pattern, then the cut feature is assigned to the second cut pattern.

17. The method of claim 9 , further comprising, further decomposing the first cut pattern into a third cut pattern and a fourth cut pattern.

18. A method comprising:
receiving a target pattern;
receiving a set of constraints, the set of constraints being associated with decomposition of the target pattern into a main pattern, a first cut pattern associated with a first mask, and a second cut pattern associated with a second mask;
with a computing system, checking the target pattern for compliance with a first constraint of the set of constraints, the first constraint associated with the first cut pattern;
with the computing system, checking the target pattern for compliance with a second constraint of the set of constraints, the second constraint associated with the second cut pattern, the second constraint being different than the first constraint;
with the computing system, modifying the pattern to create a modified target pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking; and
fabricating, with the first mask and the second mask, an integrated circuit associated with the modified target pattern.

19. The method of claim 18 , wherein the first constraint is a keep-out-zone indicating a region surrounding a cut feature in which another cut feature should not be placed.

20. The method of claim 1 , wherein the first constraint is a keep-out-zone indicating a region surrounding a cut feature, wherein the cut feature should not be placed such that an end of a main feature is within a keep-out-zone associated with the cut feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Huang-Yu
• Hou Yuan-Te
• Kao Yu-Hsiang
• Hsieh Ken-Hsien
• Liu Ru-Gun
• Lu Lee-Chung

Classifications

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2111/06

  Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA] · CPC title

• G03F7/0035

  Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title