Determining slack estimates for multiple instances of a cell in a hierarchical circuit design

Patent metadata

Field	Value
Publication number	US-9754069-B2
Application number	US-201514885920-A
Country	US
Kind code	B2
Filing date	Oct 16, 2015
Priority date	Oct 16, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. Timing context information is determined for each instance of the cell included in the circuit. A merged timing context information is determined to bound and cover each of the plurality of instances of the cell. A slack estimate is determined for a pair of ports for each instance of the cell. The instance with the smallest slack estimate is identified. A slack estimate for a pair of ports of the cell is determined based on the merged timing information of the cell. A timing credit is determined for the pair of ports based on the slack of the instance with the smallest slack and the slack estimate from the bound information for the pair of ports.

First claim

What is claimed is:

1. A method for performing static timing analysis comprising:
receiving digital representation of a circuit, the digital representation of the circuit including a plurality of instances of a cell, the cell having a plurality of ports, the digital representation of the circuit for subsequent design and manufacturing of a circuit;
receiving timing context information for each of the plurality of instances of the cell;
determining a slack estimate for pair of ports for each of the plurality of instances of the cell;
identifying an instance of the plurality of instances of the cell with a smallest slack estimate;
determining a bound on the slack estimate for a pair of ports of the cell based on the timing context information for each of the plurality of instances of the cell;
determining, by a computer, a timing credit for the pair of ports of the cell based on the slack of the instance with the smallest slack and the bound on the slack estimate for the pair of ports;
determining, by the computer, a slack estimate for the pair of ports of the cell by adjusting the bound on the slack estimate for the pair based on the timing credit for the pair; and
performing static timing analysis of the circuit based on the determined slack estimate.

2. The method of claim 1 , wherein the pair of ports of the cell comprises a data input port and a clock input port, and wherein the timing context information of each instance includes:
a data timing window for input data arrival for the data input port, and
a clock timing window for clock arrival for the clock input port.

3. The method of claim 2 , wherein determining a slack for an instance of the cell comprises:
determining an end of the data timing window for input data arrival of the data input port;
determining a start of the clock timing window for clock arrival of the clock input port; and
determining the slack estimate based on the determined start of the clock timing window for clock arrival and the end of the data timing window for input data arrival.

4. The method of claim 2 , wherein determining a bound on the slack estimate for the port pair comprises:
determine a merged data timing window for the data input port, the merged data timing window based on the data timing window for the data input port for each of the instances of the cell; and
determining a merged clock timing window for the clock input port, the merged clock timing window based on the clock timing window for the clock input port for each of the instance of the cell.

5. The method of claim 4 , wherein:
the merged data timing window for the data input port includes every data timing window for the data input port of each of the instances of the cell; and
the merged clock timing window for the clock input port includes every clock timing window for the clock input port of each of the instances of the cell.

6. The method of claim 2 , further comprising:
storing an association between the credit, the data input port, and the clock input port.

7. The method of claim 1 , wherein the pair of ports of the cell comprises a first clock input port and a second clock input port, wherein the timing context information of each instance includes:
a first clock timing window for clock arrival for the first clock input port, and
a second clock timing window for clock arrival for the second clock input port; and
wherein determining a slack for an instance of the cell comprises:
determining an end of the first clock timing window for clock arrival of the first clock input port,
determining a start of the second clock timing window for clock arrival of the second clock input port, and
determining the slack based on the determined start of the second clock timing window and the determined end of the first clock timing window.

8. The method of claim 1 , wherein determining the credit for the cell comprises:
determining a difference between the slack estimate for the pair of ports for the instance with the smallest slack and the bound on slack estimates for the pair of ports of the cell.

9. The method of claim 8 , further comprising:
storing an association between the timing credit value, the first clock input port, and the second clock input port.

10. The method of claim 1 , wherein the digital representation of the circuit is for manufacturing the circuit.

11. A non-transitory computer readable storage medium storing instructions, the instruction when executed by a processor cause the processor to:
receive digital representation of a circuit, the digital representation of the circuit including a plurality of instances of a cell, the cell having a plurality of ports;
receive timing context information for each of the plurality of instances of the cell, the digital representation of the circuit for subsequent design and manufacturing of a circuit;
determine a slack estimate for pair of ports for each of the plurality of instances of the cell;
identify an instance of the plurality of instances of the cell with a smallest slack estimate;
determine a bound on the slack estimate for a pair of ports of the cell based on the timing context information for each of the plurality of instances of the cell;
determine a timing credit for the pair of ports of the cell based on the slack of the instance with the smallest slack and the bound on the slack estimate for the pair of ports;
determine a slack estimate for the pair of ports of the cell by adjusting the bound on the slack estimate for the pair based on the timing credit for the pair; and
perform static timing analysis of the circuit based on the determined slack estimate.

12. The non-transitory computer readable storage medium of claim 11 :
wherein the pair of ports of the cell comprises a data input port and a clock input port, and wherein the timing context information of each instance includes:
a data timing window for input data arrival for the data input port, and
a clock timing window for clock arrival for the clock input port; and

wherein the instructions for determining a slack for an instance of the cell, when executed by the processor, cause the processor to:
determine an end of the data timing window for input data arrival of the data input port;
determine a start of the clock timing window for clock arrival of the clock input port; and
determine the slack estimate based on the determined start of the clock timing window for clock arrival and the end of the data timing window for input data arrival.

13. The non-transitory computer readable storage medium of claim 12 , wherein the instructions for determining a bound on the slack estimate for the port pair, when executed by the processor, cause the processor to:
determine a merged data timing window for the data input port, the merged data timing window based on the data timing window for the data input port for each of the instances of the cell wherein the merged data timing window for the data input port includes every data timing window for the data input port of each of the instances of the cell, and
determine a merged clock timing window for the clock input port, the merged clock timing window based on the clock timing window for the clock input port for each of the instance of the cell, wherein the merged clock timing window for the clock input port includes every clock timing window for the clock input port of each of the instances of the cell.

14. The non-transitory computer readable storage medium of claim 11 , wherein the pair of ports of the cell comprises a first clock input port and a second clock input port, wherein the timing context information o

Assignees

• Synopsys Inc

Inventors

• Wu Qiuyang
• Zhao Chang

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F17/5081 Primary

  Physics · mapped topic