Page table entry consolidation

Patent metadata

Field	Value
Publication number	US-9753860-B2
Application number	US-201213517738-A
Country	US
Kind code	B2
Filing date	Jun 14, 2012
Priority date	Jun 14, 2012
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Embodiments relate to managing page table entries in a processing system. A first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses is identified. The page table includes a second page table entry contiguous with the second page table entry. It is determined whether the first PTE may be joined with the second PTE based on the respective pages of main storage being contiguous. A marker is set in the page table for indicating that the main storage pages identified by the first PTE and second PTEs are contiguous.

First claim

What is claimed is:

1. A computer program product for managing page table entries in a processing system, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
identifying, by a processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the page table comprising a second PTE contiguous with the first page table entry;
determining with the processor whether the first PTE may be joined with the second PTE, the determining based on the respective first page and second page of main storage being contiguous, the determining including confirming that the first PTE and the second PTE are valid; and
setting a respective marker in each of the first PTE and the second PTE in the page table for indicating that the main storage pages identified by the first PTE and the second PTE are contiguous, wherein the first PTE and the second PTE each comprise a respective physical address field, and wherein a first value that is stored in the physical address field of the first PTE is different from a second value that is stored in the physical address field of the second PTE.

2. The computer program product of claim 1 , wherein the method further comprises executing a translation lookaside buffer (TLB) invalidate instruction for invalidating TLB entries associated with the first PTE and second PTE.

3. The computer program product of claim 1 , wherein the method further comprises starting a memory access routine for a first virtual address stored in the first page table entry (PTE) in the page table, wherein the memory access routine performs:
locating the first PTE in the page table;
determining with the processor whether the marker associated with the first PTE is set;
identifying a large page size of a large page associated with the page table based on determining that the marker is set in the first PTE, wherein the large page consisting of contiguous pages comprising said first page and said second page;
identifying a third PTE that is distinct from the first PTE and the second PTE, wherein the third PTE points to a third page that is contiguous to the first page and the second page and comprises a physical address field that stores a start location of the large page comprising the first page, second page, and third page based on determining that the marker associated with the first PTE is set; and
obtaining a physical address of the large page of main storage identified by the third PTE that points to the start location of the large page from the physical address field located in the third PTE based on determining that the marker associated with the first PTE is set;
wherein additional page properties of the large page comprise the first value and the second value that are stored in the physical address field in the first PTE and in the physical address field in the second PTE, and further comprising obtaining the additional page properties of the large page from the physical address field located in the first PTE and the physical address field located in the second PTE.

4. The computer program product of claim 3 , wherein the method further comprises:
storing translation information, marker information and said physical address in a TLB; and
using said stored translation information to translate virtual addresses associated with the large page.

5. The computer program product of claim 3 , wherein the marker is set in a plurality of PTEs indicating the main storage pages identified by the plurality of PTEs are contiguous, the plurality of PTEs comprising each of the first PTE, the second PTE, and the third PTE.

6. The computer program product of claim 1 , wherein the PTEs are any one of third PTEs in page tables of a hierarchy of translation tables, or fourth PTEs in a group of PTEs, each fourth PTE having a field identifying an associated virtual address.

7. A computer system for accessing a memory location, the system comprising:
a memory; and
a processor coupled to the memory, the computer system configured to perform a method comprising:
identifying, with the processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the page table comprising a second PTE contiguous with the first page table entry;
determining, with the processor, whether the first PTE may be joined with the second PTE, the determining based on the respective first page and second page of main storage being contiguous, the determining including confirming that the first PTE and the second PTE are valid; and
setting a respective marker in each of the first PTE and the second PTE in the page table for indicating that the main storage pages identified by the first PTE and the second PTE are contiguous, wherein the first PTE and the second PTE each comprise a respective physical address field, and wherein a first value that is stored in the physical address field of the first PTE is different from a second value that is stored in the physical address field of the second PTE.

8. The system of claim 7 , wherein the method further comprises executing a translation lookaside buffer (TLB) invalidate instruction for invalidating TLB entries associated with the first PTE and second PTE.

9. The system of claim 7 , wherein the method further comprises starting a memory access routine for a first virtual address stored in the first page table entry (PTE) in the page table, wherein the memory access routine performs:
locating the first PTE in the page table;
determining with the processor whether the marker associated with the first PTE is set;
identifying a third PTE that is distinct from the first PTE and the second PTE, wherein the third PTE points to a third page that is contiguous to the first page and the second page and comprises a physical address field that stores a start location of the large page comprising the first page, second page, and third page based on determining that the marker associated with the first PTE is set; and
obtaining a physical address of the large page of main storage identified by the third PTE that points to the start location of the large page from the physical address field located in the third PTE based on determining that the marker associated with the first PTE is set;
wherein additional page properties of the large page comprise the first value and the second value that are stored in the physical address field in the first PTE and in the physical address field in the second PTE, and further comprising obtaining the additional page properties of the large page from the physical address field located in the first PTE and the physical address field located in the second PTE.

10. The system of claim 9 , wherein the method further comprises:
storing translation information, marker information and said physical address in a TLB; and
using said stored translation information to translate virtual addresses associated with the large page.

11. The system of claim 9 , wherein the marker is set in a plurality of PTEs indicating the main storage pages identified by the plurality of PTEs are contiguous, the plurality of PTEs comprising each of the first PTE, the second PTE, and the third PTE.

12. The system of claim 7 , wherein the PTEs are any one of third PTEs in page tables of a hierarchy of translation tables, or fourth PTEs in a group of PTEs, each fourth PTE having a field identifying an associated virtual address.

Assignees

• Bybell Anthony J
• Gschwind Michael K
• IBM

Inventors

• Bybell Anthony J
• Gschwind Michael K

Classifications

• G06F2212/652

  Page size control · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title