Methods and systems for managing address list control blocks

Patent metadata

Field	Value
Publication number	US-9753852-B1
Application number	US-201514919508-A
Country	US
Kind code	B1
Filing date	Oct 21, 2015
Priority date	Oct 21, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Methods and systems for a device coupled to a computing device are provided. As an example, one method includes receiving a request for processing an address list control block (ALCB) by an ALCB offload engine of an adapter coupled to a computing device; determining by the ALCB offload engine if the ALCB is located at a cache managed by a cache controller of the ALCB engine; forwarding the ALCB to an address computation module that determines an address of a memory location of the computing device, where the ALCB stores the address of the memory location in an address list; generating a direct memory access (DMA) request to retrieve the ALCB from an adapter memory, when the ALCB is not located at the cache; and storing the ALCB at the cache, after the ALCB is received in response to the DMA request.

First claim

What is claimed is:

1. A machine implemented method, comprising:
receiving a request for processing an address list control block (ALCB) by a hardware based, ALCB offload engine of an adapter coupled to a computing device, where the ALCB is for sending information by the adapter to a processor of the computing device;
determining by the ALCB offload engine that the ALCB associated with the request is located at a cache of the ALCB offload engine that is managed by a cache controller of the ALCB offload engine;
forwarding the ALCB to an address computation module of the ALCB offload engine that uses the ALCB to compute an address of a memory location of the computing device for transferring the information to the processor of the computing device, where the ALCB stores the address of the memory location in an address list;
generating a direct memory access (DMA) request to retrieve the ALCB from an adapter memory location, when the ALCB is not located at the cache; and
storing the ALCB at the cache, after the ALCB is received in response to the DMA request; wherein the ALCB stored at the cache is used for ALCB processing by the ALCB offload engine for another request received after the ALCB is stored at the cache; and

wherein the ALCB offload engine offloads ALCB processing from a receive direct memory access (RxDMA) module of the adapter that transfers the information to the processor of the computing device.

2. The method of claim 1 , wherein the cache controller uses a memory region identifier and a block identifier as an index to determine if the ALCB is stored at the cache.

3. The method of claim 1 , wherein the ALCB offload engine uses a ternary content addressable memory (TCAM) that stores a tag for each cache entry with a valid bit indicating that a cache entry is valid, a dirty bit indicating that a cache entry is to be written to the adapter memory and a transit bit indicating that a cache entry is in use.

4. The method of claim 1 , wherein when the cache does not have space for the ALCB retrieved in response to the DMA request, then the cache controller flushes a least recently used entry to the adapter memory to create space for the ALCB.

5. The method of claim 1 , wherein the adapter is a host bus adapter configured to process input/output requests.

6. The method of claim 3 , wherein the request for the ALCB is generated by processing logic of the adapter.

7. The method of claim 1 , wherein the request is stored at a first in-first out memory device and retrieved by the cache controller for processing.

8. A non-transitory, machine readable storage medium having stored thereon instructions for performing a method, comprising machine executable code which when executed by at least one machine, causes the machine to:
receive a request for processing an address list control block (ALCB) by a hardware based, ALCB offload engine of an adapter coupled to a computing device, where the ALCB is for sending information by the adapter to a processor of the computing device;
determine by the ALCB offload engine that the ALCB associated with the request is located at a cache of the ALCB offload engine that is managed by a cache controller of the ALCB offload engine;
forward the ALCB to an address computation module of the ALCB offload engine that uses the ALCB to compute an address of a memory location of the computing device for transferring the information to the processor of the computing device, where the ALCB stores the address of the memory location in an address list;
generate a direct memory access (DMA) request to retrieve the ALCB from an adapter memory location, when the ALCB is not located at the cache; and
store the ALCB at the cache, after the ALCB is received in response to the DMA request; wherein the ALCB stored at the cache is used for ALCB processing by the ALCB offload engine for another request received after the ALCB is stored at the cache; and wherein the ALCB offload engine offloads ALCB processing from a receive direct memory access (RxDMA) module of the adapter that transfers the information to the processor of the computing device.

9. The non-transitory, storage medium of claim 8 , wherein the cache controller uses a memory region identifier and a block identifier as an index to determine if the ALCB is stored at the cache.

10. The non-transitory, storage medium of claim 8 , wherein the ALCB offload engine uses a ternary content addressable memory (TCAM) that stores a tag for each cache entry with a valid bit indicating that a cache entry is valid, a dirty bit indicating that a cache entry is to be written to the adapter memory and a transit bit indicating that a cache entry is in use.

11. The non-transitory, storage medium of claim 8 , wherein when the cache does not have space for the ALCB retrieved in response to the DMA request, then the cache controller flushes a least recently used entry to the adapter memory to create space for the ALCB.

12. The non-transitory, storage medium of claim 8 , wherein the adapter is a host bus adapter configured to process input/output requests.

13. The non-transitory, storage medium of claim 12 , wherein the request for the ALCB is generated by processing logic of the adapter.

14. The non-transitory, storage medium of claim 8 , wherein the request is stored a first in-first out memory device and retrieved by the cache controller for processing.

15. A device coupled to a computing device, comprising:
processing logic for executing instructions out of a device memory and generating a request for processing an address list control block (ALCB) used for sending information to a processor of the computing device; and
a hardware based ALCB offload engine having:
a cache controller that is configured to receive the request for processing the ALCB; determine that the ALCB is located at a cache of the ALCB offload engine managed by the cache controller;
forward the ALCB to an address computation module of the ALCB offload engine that uses the ALCB to compute an address of a memory location of the computing device, where the ALCB stores the address of the memory location in an address list;
generate a direct memory access (DMA) request to retrieve the ALCB from the device memory, when the ALCB is not located at the cache; and
store the ALCB at the cache, after the ALCB is received in response to the DMA request; wherein the ALCB stored at the cache is used for ALCB processing by the ALCB offload engine for another request received after the ALCB is stored at the cache; and wherein the ALCB offload engine offloads ALCB processing from a receive direct memory access (RxDMA) module of the adapter that transfers the information to the processor of the computing device.

16. The device of claim 15 , wherein the cache controller uses a memory region identifier and a block identifier as an index to determine if the ALCB is stored at the cache.

17. The device of claim 15 , wherein the ALCB offload engine uses a ternary content addressable memory (TCAM) that stores a tag for each cache entry with a valid bit indicating that a cache entry is valid, a dirty bit indicating that a cache entry is to be written to the adapter memory and a transit bit indicating that a cache entry is in use.

18. The device of claim 15 , wherein when the cache does not have space for the ALCB retrieved in response to the DMA request, then the cache controller flushes a least recently used entry to the adapter memory to create space for the ALCB.

19. The device of claim 15 , wherein the adapter is a host bus

Assignees

• Qlogic Corp

Inventors

• Konda Dharma R
• Magsino Paul R

Classifications

• G06F2212/69

  Physics · mapped topic

• G06F17/30982

  Physics · mapped topic

• G06F12/122

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title