Minimizing bandwith to compress output stream in instruction tracing systems

Patent metadata

Field	Value
Publication number	US-9753832-B2
Application number	US-201313930501-A
Country	US
Kind code	B2
Filing date	Jun 28, 2013
Priority date	Jun 28, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.

First claim

What is claimed is:

1. A processing device comprising:
an instruction tracing (IT) module to:
identify a current instruction in a trace of the IT module as a conditional branch (CB) instruction;
execute one of generate a first CB packet comprising a byte pattern with an indication of outcome of the CB instruction, or add an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet;
generate an IT packet in response to determining that a subsequent instruction in the trace after the current instruction is not the CB instruction, wherein the IT packet is different from the first CB packet or the existing CB packet;
add the IT packet into a deferred queue in response to determining that the packet is deferrable, wherein the deferred queue comprises a deferred packet;
output the first CB packet or the existing CB packet followed by the deferred packet, followed by the IT packet into a packet log in response to determining that the IT packet is not deferrable, wherein determining that the IT packet is not deferrable is based on at least one of a first or a second condition is met, wherein the first condition comprises a total number of bits in the byte pattern of the first CB packet or the existing CB packet reach a first threshold, wherein the second condition comprises a total number of packets in the deferred queue reach a second threshold.

2. The processing device of claim 1 wherein the IT packet is an indirect branch (IB) packet, wherein the IB packet provides a target location for transfer of execution associated with the instruction in the trace.

3. The processing device of claim 2 wherein the IT module to determine that the IB packet is not deferrable in response to determining that the instruction comprises an uncompressible return instruction.

4. The processing device of claim 1 wherein the IT packet is an event packet that provides an updated status of the processing device.

5. The processing device of claim 1 wherein the IT module to continue to add subsequent packets into the deferred queue in response to determining that the subsequent packets are deferrable.

6. The processing device of claim 5 wherein the deferred packets are outputted in the output log as a first in first out (FIFO) queue.

7. A system comprising:
a memory; and
a processing device communicably coupled to the memory, wherein the processing device comprising:
a scheduler and execution unit; and
a retirement unit communicably coupled to the scheduler and execution unit, the retirement unit comprising an instruction tracing (IT) module to:
identify a current instruction in a trace of the IT module as a conditional branch (CB) instruction;
execute one of generate a first CB packet comprising a byte pattern with an indication of outcome of the CB instruction, or add an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet;
generate an IT packet in response to determining that a subsequent instruction in the trace after the current instruction is not the CB instruction, wherein the IT packet is different from the first CB packet or the existing CB packet;
add the IT packet into a deferred queue in response to determining that the packet is deferrable, wherein the deferred queue comprises a deferred packet;
output the first CB packet or the existing CB packet followed by the deferred packet, followed by the IT packet into a packet log in response to determining that the IT packet is not deferrable, wherein determining that the IT packet is not deferrable is based on at least one of a first or a second condition is met, wherein the first condition comprises a total number of bits in the byte pattern of the first CB packet or the existing CB packet reach a first threshold, wherein the second condition comprises a total number of packets in the deferred queue reach a second threshold.

8. The system of claim 7 wherein the IT packet is an indirect branch (IB) packet, wherein the IB packet provides a target location for transfer of execution associated with the instruction in the trace.

9. The system of claim 8 wherein the IT module to determine that the IB packet is not deferrable in response to determining that the instruction comprises an uncompressible return instruction.

10. The system of claim 7 wherein the IT packet is an event packet that provides an updated status of the processing device.

11. The system of claim 7 wherein the IT module to continue to add subsequent packets into the deferred queue in response to determining that the subsequent packets are deferrable.

12. The system of claim 11 wherein the deferred packets are outputted in the output log as a first in first out (FIFO) queue.

13. A method of a processing device comprising:
identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction;
executing one of generate a first CB packet comprising a byte pattern with an indication of outcome of the CB instruction, or add an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet;
generating a an IT packet in response to determining that a subsequent instruction in the trace after the current instruction is not the CB instruction, wherein the IT packet is different from the first CB packet or the existing CB packet;
adding the IT packet into a deferred queue in response to determining that the packet is deferrable, wherein the deferred queue comprises a deferred packet;
outputting the first CB packet or the existing CB packet followed by the deferred packet, followed by the IT packet into a packet log in response to determining that the IT packet is not deferrable, wherein determining that the IT packet is not deferrable is based on at least one of a first or a second condition is met, wherein the first condition comprises a total number of bits in the byte pattern of the first CB packet or the existing CB packet reach a first threshold, wherein the second condition comprises a total number of packets in the deferred queue reach a second threshold.

14. The method of claim 13 , wherein the IT packet is an indirect branch (TB) packet, wherein the IB packet provides a target location for transfer of execution associated with the instruction in the trace.

15. The method of claim 14 further comprising determining that the IB packet is not deferrable in response to determining that the instruction comprises an uncompressible return instruction.

16. The method of claim 13 wherein the IT packet is an event packet that provides an updated status of the processing device.

17. The method of claim 13 further comprising continuously adding subsequent packets into the deferred queue in response to determining that the subsequent packets are deferrable.

18. The method of claim 17 wherein the deferred packets are outputted in the output log as a first in first out (FIFO) queue.

19. A non-transitory machine-readable storage medium including data that, when accessed by a processing device, cause the processing device to perform operations comprising:
identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction;
executing one of generate a first CB packet comprising a byte pattern with an indication of outcome of the CB instruction, or add an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet;
generating an IT packet in response to determining that a subsequent instruction in the trace after the current instruction

Assignees

• Intel Corp

Inventors

• Wagner Ilya
• Merten Matthew C
• Binns Frank
• Wang Christine E
• Bomb Mayank
• Li Tong
• Schmitt Thilo
• Rahman M D A

Classifications

• G06F2201/81

  Threshold · CPC title

• G06F11/3466 Primary

  Performance evaluation by tracing or monitoring · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title