Simulator generation method and apparatus

Patent metadata

Field	Value
Publication number	US-9753752-B2
Application number	US-201414279537-A
Country	US
Kind code	B2
Filing date	May 16, 2014
Priority date	Nov 18, 2011
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.

First claim

What is claimed is:

1. A method, comprising:
obtaining an instruction set configuration file;
generating a decoding table and a decoding algorithm according to the instruction set configuration file, wherein the decoding table comprises: an instruction code table, an instruction description table, and a bit field table, and assembly instruction operation code is recorded in the instruction code table, information of each piece of the assembly instruction operation code is recorded in the instruction description table, and a method for calculating a numerical value in each operand bit field is recorded in the bit field table;
generating a simulator according to the decoding table, the decoding algorithm, and module code, wherein the simulator is configured for simulating an action associated with a chip during a chip design process, wherein the module code is code used to simulate an action of an assembly instruction and code of a second algorithm in a decoding process;
performing the chip design process, wherein performing the chip design process comprises executing the simulator code to simulate the action; and
manufacturing the chip according to the chip design process.

2. The method according to claim 1 , wherein the instruction set configuration file comprises: an assembly output format, a type of an operand, and a coding format of each instruction, wherein each instruction comprises: an operand and operation code; and
generating a decoding table according to the instruction set configuration file comprises:
generating the instruction code table according to the operation code of each instruction;

generating the instruction description table according to the assembly output format, the type of the operand, and the coding format of each instruction; and
generating the bit field table according to the operand of each instruction.

3. The method according to claim 2 , wherein generating the instruction code table according to the operation code of each instruction comprises:
generating layered instruction code tables according to an operation code bit field of each instruction and a value of each operation code bit field.

4. The method according to claim 2 , wherein the decoding algorithm comprises: an algorithm for obtaining assembly instruction operation code, an algorithm for obtaining relevant information of the assembly instruction operation code, and an algorithm for obtaining an assembly instruction operand; and
generating a decoding algorithm according to the instruction set configuration file comprises:
generating, according to a rule for generating the instruction code table by using the instruction set configuration file, an algorithm for obtaining assembly instruction operation code for a decoding algorithm used to search for assembly instruction operation code corresponding to binary instruction operation code in the instruction code table;
generating, according to a rule for generating the instruction description table by using the instruction set configuration file, and an index relationship between the instruction code table and the instruction description table, an algorithm for obtaining relevant information of assembly instruction operation code for a decoding algorithm used to index the instruction description table according to the assembly instruction operation code and read relevant information of the assembly instruction operation code in the indexed instruction description table; and
generating, according to a rule for generating the bit field table by using the instruction set configuration file, and an index relationship between the instruction description table and the bit field table, an algorithm for obtaining an assembly instruction operand for a decoding algorithm used to index the bit field table according to the relevant information of the assembly instruction operation code and calculate the assembly instruction operand according to the indexed bit field table.

5. The method according to claim 4 , wherein the decoding table further comprises: an indirect index table in an index relationship with the instruction code table; and
generating, according to a rule for generating the instruction code table by using the instruction set configuration file, an algorithm for obtaining assembly instruction operation code for a decoding algorithm used to search for assembly instruction operation code corresponding to binary instruction operation code in the instruction code table comprises:
generating, according to a rule for generating the instruction code table and the indirect index table by using the instruction set configuration file, and the index relationship between the instruction code table and the indirect index table, the algorithm for obtaining assembly instruction operation code for the decoding algorithm used to search for assembly instruction operation code corresponding to binary instruction operation code in the instruction code table.

6. The method according to claim 1 , wherein in a same instruction set configuration file, one instruction exists in one instruction set or in at least two different instruction sets.

7. An apparatus, comprising:
an obtaining unit, configured to obtain an instruction set configuration file;
an interpreter, configured to generate a decoding table and a decoding algorithm according to the instruction set configuration file, wherein the decoding table comprises: an instruction code table, an instruction description table, and a bit field table, and assembly instruction operation code is recorded in the instruction code table, information of each piece of the assembly instruction operation code is recorded in the instruction description table, and a method for calculating a numerical value in each operand bit field is recorded in the bit field table; and
a compiler, configured to generate a simulator according to the decoding table, the decoding algorithm, and module code, wherein the simulator is configured for simulating an action associated with a chip during a chip design process, wherein the module code is code used to simulate an action of an assembly instruction and code of a second algorithm in a decoding process,
wherein the apparatus is configured to perform the chip design process and manufacture the chip according to the chip design process, wherein performing the chip design process comprises executing the simulator code to simulate the action.

8. The apparatus according to claim 7 , wherein:
the instruction set configuration file comprises: an assembly output format, a type of an operand, and a coding format of each instruction, wherein each instruction comprises: an operand and operation code; and
the interpreter is configured to generate the decoding table according to the instruction set configuration file and comprises:
an instruction code table generation module, configured to generate the instruction code table according to the operation code of each instruction;
an instruction description table generation module, configured to generate the instruction description table according to the assembly output format, the type of the operand, and the coding format of each instruction; and
a bit field table generation module, configured to generate the bit field table according to the operand of each instruction.

9. The apparatus according to claim 8 , wherein the instruction code table generation module is configured to:
generate layered instruction code tables according to an operation code bit field of each instruction and a value of each operation code bit field.

10. The apparatus according to claim 8 , wherein the decoding algorithm generated by the interpreter comprises: an algorithm for obtaining assem

Assignees

• Huawei Tech Co Ltd

Inventors

• Ye Handong
• Zhao Peng
• Zheng Senhuo
• Cao jiong

Classifications

• G06F8/53

  Decompilation; Disassembly · CPC title

• G06F8/30 Primary

  Creation or generation of source code · CPC title

• G06F9/4552

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title

• G06F2117/08

  HW-SW co-design, e.g. HW-SW partitioning · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title