Methods and systems for analyzing and improving performance of computer codes

Patent metadata

Field	Value
Publication number	US-9753731-B1
Application number	US-201514598565-A
Country	US
Kind code	B1
Filing date	Jan 16, 2015
Priority date	Jan 16, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Methods and systems for analyzing and improving performance of computer codes. In some embodiments, a method comprises executing, via one or more processors, program code; collecting, via the one or more processors, one or more hardware dependent metrics for the program code; identifying an execution anomaly based on the one or more hardware dependent metrics, wherein the execution anomaly is present when executing the program code; and designing a modification of the program code via the one or more processors, wherein the modification addresses the execution anomaly. In some other embodiments, a method comprises collecting one or more hardware independent metrics for program code; receiving one or more characteristics of a computing device; and estimating, based on the one or more hardware independent metrics and the one or more characteristics, a duration for execution of the program code on the computing device.

First claim

The invention claimed is:

1. A method comprising:
executing, via one or more processors, program code for a plurality of times;
collecting, via the one or more processors, one or more values of one or more hardware dependent metrics for the program code, the one or more hardware dependent metrics including a first hardware dependent metric and a second hardware dependent metric;
measuring one or more changes in values of the one or more hardware dependent metrics during the executing of the program code for the plurality of times, including a first change in value of the first hardware dependent metric and a second change in value of the second hardware dependent metric;
identifying an execution anomaly based on the one or more changes in values of the one or more hardware dependent metrics wherein:
the one or more changes in values of the one or more hardware dependent metrics each correspond to an increase or a decrease in one or more values of the one or more hardware dependent metrics during the executing of the program code for the plurality of times;
the first change in value of the first hardware dependent metric is correlated to the second change in value of the second hardware dependent metric;
the first change in value of the first hardware dependent metric and the second change in value of the second hardware dependent metric result from the executing, for the plurality of times, of one or more instructions of the program code;

the execution anomaly relates to a hardware related optimization used when executing the one or more instructions of the program code, that causes an overall performance issue in the executing of the program code; and

modifying the program code, wherein the modifying removes the execution anomaly from the program code and improves the overall performance issue in the executing of the program code wherein the overall performance issue comprises a slow down in executing the program code, and improving the overall performance issue comprises speeding up the executing of the program code.

2. The method of claim 1 , wherein the one or more values of the one or more hardware dependent metrics include at least one of:
a number of instructions retired;
a number of cache hits;
a number of cache misses;
a number of branch mispredictions; and
a number of cycles.

3. The method of claim 1 , wherein the modification includes one or more of:
reordering a section of the program code;
introducing a delay in the program code;
reordering access to data structures in a memory; and
reducing a number of branch conditions.

4. The method of claim 1 , wherein the execution anomaly includes a timing anomaly compromising:
a fluctuation in a duration of executing a part of the program code.

5. The method of claim 4 , wherein the timing anomaly includes a delay in executing the program code;
and the method further comprises:
addressing the timing anomaly, wherein the addressing reduces the delay.

6. The method of claim 1 , wherein identifying the execution anomaly includes identifying a memory event associated with the program code.

7. The method of claim 6 , wherein the memory event includes a cache miss associated with a section of the program code.

8. The method of claim 1 , wherein identifying the execution anomaly includes identifying a branch misprediction.

9. A non-transitory computer-readable medium storing instructions for one or more processors to execute a method comprising:
executing, via one or more processors, program code for a plurality of times;
collecting, via the one or more processors, one or more values of one or more hardware dependent metrics for the program code, the one or more hardware dependent metrics including a first hardware dependent metric and a second hardware dependent metric;
measuring one or more changes in values of the one or more hardware dependent metrics during the executing of the program code for the plurality of times, including a first change in value of the first hardware dependent metric and a second change in value of the second hardware dependent metric;
identifying an execution anomaly based on the one or more changes in values of the one or more hardware dependent metrics wherein:
the one or more changes in values of the one or more hardware dependent metrics each correspond to an increase or a decrease in one or more values of the one or more hardware dependent metrics during the executing of the program code for the plurality of times;
the first change in value of the first hardware dependent metric is correlated to the second change in value of the second hardware dependent metric;
the first change in value of the first hardware dependent metric and the second change in value of the second hardware dependent metric result from the executing, for the plurality of times, of one or more instructions of the program code;

the execution anomaly relates to a hardware related optimization used when executing the one or more instructions of the program code, that causes an overall performance issue in the executing of the program code; and

modifying the program code, wherein the modifying removes the execution anomaly from the program code and improves the overall performance issue in the executing of the program code wherein the overall performance issue comprises a slow down in executing the program code, and improving the overall performance issue comprises speeding up the executing of the program code.

10. A method comprising:
collecting one or more values of one or more hardware independent metrics for program code wherein the one or more values of the one or more hardware independent metrics include total number of instructions, probability of floating point instruction, cycles to execute floating point instruction, number of integer instructions between floating point instructions, probability of integer instruction, and cycles to execute integer instruction;
receiving one or more hardware characteristics of a computing device;
estimating, based on the one or more values of the one or more hardware independent metrics, total execution cycles for the program code wherein the estimating includes:
calculating a first estimated number for execution cycles for executing floating instructions in the program code;
calculating a second estimated number for execution cycles for executing integer instructions in the program code;
combining the first estimated number and the second estimated number;
estimating, based on the one or more hardware characteristics, a time per execution cycle for the program code; and
estimating, based on the total execution cycles and the time per execution cycle, a duration for execution of the program code on the computing device;
choosing, based on the estimated duration for execution of the program code on the computing device, a hardware architecture that will meet a desired execution duration
executing the program code on the chosen hardware architecture.

11. The method of claim 10 , wherein the one or more hardware independent metrics include at least one of:
an instruction mix;
an instruction-level parallelism factor;
a register traffic;
a working-set size;
a data stream stride;
and a branch ability.

12. The method of claim 10 , wherein the one or more hardware characteristics include one or more of:
a number of cores;
a core frequency;
a bus type;
a bus speed;
and a memory hierarchy.

13. The method of claim 12 , wherein the memory hierarchy includes one or more of:
a number of cache levels;
a size of caches;
a cache eviction policy,
a type of caches,
a size of main memory;
and a c

Assignees

• Mathworks Inc

Inventors

• Puzovic Milos

Classifications

• G06F8/4441 Primary

  Reducing the execution time required by the program code · CPC title

• G06F11/3495

  for systems · CPC title

• G06F9/30181 Primary

  Instruction operation extension or modification · CPC title

• G06F11/3428

  Benchmarking · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title