Datapath circuit for digital signal processors

Patent metadata

Field	Value
Publication number	US-9753695-B2
Application number	US-201314010946-A
Country	US
Kind code	B2
Filing date	Aug 27, 2013
Priority date	Sep 4, 2012
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

First claim

The invention claimed is:

1. A processing system, comprising:
an input data register to store input operand data;
a digital multiply and accumulate (MAC) system and a calculator system each having inputs coupled to the input data register, wherein:
the MAC system comprises a multiplier stage and an adder stage; and
the calculator system comprises a look-up table operatively coupled to the input data register, the look-up table having a plurality of entries mapped to by candidate input operand data, the entries storing corresponding pre-calculated results of a predetermined mathematical function performed on the candidate input operand data and the look-up table having an output connected to an input of the adder stage, the output configured to provide a result of the predetermined mathematical function from a table entry;

wherein the look-up table comprises a readable and writable memory storing the plurality of entries and the corresponding pre-calculated results, the readable and writeable memory supporting run-time changes to the predetermined mathematical function.

2. The system of claim 1 , wherein:
the look-up table has fewer entries than are possible under all variations of input operand data;
the look-up table has a pair of outputs to output a pair of table entries that map most closely to an input operand when the input operand does not map to any entry of the look-up table exactly; and
the calculator system further comprises an interpolator coupled to the outputs of the look-up table.

3. The system of claim 1 , wherein the look-up table comprises N-dimensions mapping respective N−1 pluralities of entries to corresponding pre-calculated results of the predetermined mathematical operation, wherein N is a positive integer larger than 2.

4. The system of claim 1 , wherein
a first input operand comprises an N-bit multiplicand and a second input operand comprises an M-bit multiplier;
the MAC system being adapted to select respective partial products of the N-bit multiplicand, where each partial product is selected from a set of partial product results computed from the N-bit multiplicand in dependence of a predetermined set of bits of the M-bit multiplier in accordance with a predetermined coding scheme;
each of M and N representing a positive integer number.

5. The system of claim 1 , wherein the calculator system further comprises a second look-up table operatively coupled between an output of the first look-up table and a calculator output register, the second look-up table comprising a plurality of entries mapped to a plurality of corresponding pre-calculated results in accordance with a second predetermined mathematical function.

6. The system of claim 4 , wherein the predetermined coding scheme comprises a Booth coding scheme selected from a group of {radix-8, radix-16, radix-32, radix-64, radix-128}Booth coding.

7. The system of claim 1 , further comprising a multiplexer having a pair of inputs, one coupled to the input data register and the other coupled to an output of the calculator system, and an output coupled to an input of the adder stage.

8. The system of claim 1 , wherein computational cycles executed by the MAC system at least partly overlap in time with computational cycles executed by the calculator system.

9. The system of claim 1 , further comprising:
a data compressor having an input coupled to the input data register, the data compressor configured to map a numerical range of the input operand data into a smaller numerical range of the input operand data; and
a compression multiplexer having inputs operatively coupled to the input data register and the data compressor, the compression multiplexer configured to selectively transmit, to an input of the look-up table, input operand data and corresponding compressed values of the input operand data.

10. The system of claim 1 , wherein the multiplier stage and the adder stage are configured in a cascade arrangement.

11. The system of claim 1 , wherein the predetermined mathematical function includes at least one function selected from the list including a logarithm function, an exponent function, a division function, and a square root function.

12. The system of claim 1 , wherein digital multiply and accumulate (MAC) system and a calculator system are configured for parallel computation.

13. A method of performing a mathematical calculation involving first and second predetermined mathematical functions, the first mathematical function being a multi -bit multiplication, comprising:
wherein the multi-bit multiplication is performed by a multiply and accumulate (MAC) system and the second predetermined mathematical function is performed by a separate calculator system;
wherein the processing includes, in the calculator system:
inputting at least one operand of the second predetermined mathematical function to a look-up table that stores pre-calculated results of the second predetermined mathematical function mapped to a plurality of candidate input operands, wherein pre-calculated results represent values of the second predetermined mathematical function performed on the candidate input operands, and
outputting from the look-up table a result of the second predetermined mathematical function from a table entry mapped to by the at least one inputted operand; and
adding the result output from the look-up table to a value obtained by the MAC system based on the multi-bit multiplication; and

wherein the pre-calculated results of the second predetermined mathematical function are stored in a readable and writable memory, the readable and writable memory configured to support run-time changes to the second predetermined mathematical function.

14. The method of claim 13 , wherein, when the inputted operand does not map to any entry of the look-up table exactly, the outputting includes outputting from the look-up table a pair of results related to candidate input operands closest to the inputted operand,
the method further comprising interpolating a result for the second predetermined mathematical function at the inputted operand from the outputted pair of results.

15. The method of claim 13 , further comprising, when the result outputted from the look-up table exceeds a predetermined limit of result data, setting the result data to a value associated with the predetermined limit.

16. The method of claim 13 , wherein the second predetermined mathematical function includes at least one function selected from the list including a logarithm function, an exponent function, a division function, and a square root function.

17. The method of claim 13 , wherein the look-up table has fewer entries than are possible under all variations of input operand data; and
wherein the method comprises interpolating between entries from the look-up table to provide the result of the second predetermined mathematical function.

18. The method of claim 17 , wherein the look-up table comprises N-dimensions mapping respective N−1 pluralities of entries to corresponding pre-calculated results of the second predetermined mathematical operation, wherein N is a positive integer larger than 2.

19. The method of claim 17 , wherein the calculator system further comprises a second look-up table operatively coupled between an output of the first look-up table and a calculator output register, the second look-up table comprising a plurality of entries mapped to a plurality of corresponding pre-calculated results in accordance with a third predetermined mathematical function.

Assignees

• Analog Devices Global

Inventors

• Mortensen Mikael M
• Bernstein Jeffrey G

Classifications

• G06F2101/10

  Logarithmic or exponential functions · CPC title

• G06F7/57 Primary

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F2101/08

  Powers or roots · CPC title

• G06F1/035

  Reduction of table size {(G06F1/0314 takes precedence)} · CPC title

• G06F7/60 Primary

  Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations {, e.g. using difunction pulse trains, STEELE computers, phase computers (conversion of digital data to or from non-denominational form H03M5/00, H03M7/00)} · CPC title