Method, apparatus, and system for energy efficiency and energy conservation by mitigating performance variations between integrated circuit devices

Patent metadata

Field	Value
Publication number	US-9753516-B2
Application number	US-201113335628-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.

First claim

What is claimed is:

1. An integrated circuit device comprising:
at least one processor core; and
a control unit coupled to the at least one processor core, the control unit to control an operating setting for the integrated circuit device by controlling an operating frequency of the at least one processor core based on an estimated activity level and an activity limit, the estimated activity level being independent of leakage power and voltage characteristics particular to the integrated circuit device, wherein the estimated activity level is based on a number of events of particular types detected upon which weighting factors have been applied depending on the complexity and amount of processing needed for a type of instruction, one of these events being a number of clock cycles and one of these events being a count of a number of different types of instructions executed, wherein the control unit is to determine a limit in the operating frequency by comparing the estimated activity level to the activity limit for a stock-keeping unit (SKU) in which the integrated circuit device is assigned, wherein the activity limit of the SKU guarantees that the integrated circuit device will stay within a power budget.

2. The integrated circuit device of claim 1 further comprising:
a ring interconnect coupled to the at least one processor core and the control unit;
a graphics logic coupled to the ring interconnect.

3. The integrated circuit device of claim 2 , wherein the control unit is located on a first power plane, memory and the at least one processor core are located on a second power plane, and the graphics logic is located on a third power plane.

4. The integrated circuit device of claim 1 , wherein the activity limit is to be computed by taking into account worst case conditions for voltage and leakage power for devices within the stock-keeping unit (SKU) in which the integrated circuit device is assigned.

5. The integrated circuit device of claim 1 , wherein the control unit is a system agent positioned on a different power plane than the at least one processor, the system agent includes a micro-controller that is to run firmware for controlling power management of power planes of the integrated circuit device based on activity that is based on detected events, weighting associated with the detected events for the integrated circuit device.

6. The integrated circuit device of claim 1 , wherein the control unit is situated on a separate integrated circuit than the at least one processor, both the control unit and the at least one processor being implemented within a single integrated circuit package.

7. The integrated circuit device of claim 1 , wherein the control unit is situated on a separate integrated circuit than the at least one processor, both the control unit and the at least one processor being implemented on a single circuit board.

8. An electronic device comprising:
a housing;
a display unit including a liquid crystal display; and
an integrated circuit device implemented with the housing, the integrated circuit device comprises at least one processor core, and a control unit coupled to the at least one processor core, the control unit to control an operating setting for the integrated circuit device by controlling an operating frequency of at least one compute engine of the at least one processor core based on an estimated activity level, the estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to the integrated circuit device, wherein the estimated activity level utilized by the integrated circuit device is based on a count of a number of different types of instructions executed upon which weighting factors have been applied depending on the complexity and amount of processing needed for the type of instruction, wherein the control unit to determine a maximum increase in the operating frequency by comparing the estimated activity level to an activity limit for a stock-keeping unit (SKU) in which the integrated circuit device is assigned, wherein the activity limit of the SKU guarantees that the integrated circuit device will stay within a power budget.

9. The electronic device of claim 8 , wherein the at least one compute engine of the integrated circuit device includes at least one processor core.

10. The electronic device of claim 8 , wherein the integrated circuit device further comprises a ring interconnect coupled to the at least one processor core and the control unit, and a graphics logic coupled to the ring interconnect.

11. The electronic device of claim 10 , wherein the control unit of the integrated circuit device comprises a micro-controller is to control power management of power planes of the integrated circuit device based on activity that is based on detected events.

12. The electronic device of claim 8 , wherein the activity limit is determined by the control unit of the integrated circuit device taking into account worst case conditions for voltage and power leakage for devices within the stock-keeping unit (SKU) in which the integrated circuit device is assigned.

13. The electronic device of claim 8 , wherein the control unit of the integrated circuit device is a system agent positioned on a different power plane than the at least one processor, the system agent includes a micro-controller that is to run firmware for controlling power management of power planes of the integrated circuit device based on activity that is based on detected events, weighting associated with the detected events and the operating frequency for the integrated circuit device.

14. A method comprising:
calculating an estimated activity level for an integrated circuit device based on a count of detected events of particular types and weightings applied to the detected events based on the complexity and amount of processing needed for a type of instruction, wherein one type of detected event is a count of a number of different types of instructions executed;
determining an activity budget for the integrated circuit device over a selected period of time for use in power conservation using the estimated activity level;
determining an operating state for the integrated circuit device based on the activity budget, the operating state being used to determine a frequency, and voltage operating point for the integrated circuit device; and
determining a maximum increase in the operating frequency by comparing the estimated activity level to an activity limit for a stock-keeping unit (SKU) in which the integrated circuit device is assigned, wherein the activity limit of the SKU guarantees that the integrated circuit device will stay within a power budget.

15. The method of claim 14 , wherein the estimated activity level is calculated internally within the integrated circuit device using information from at least one pre-programmed fuse within the integrated circuit device.

16. The method of claim 14 , wherein the operating state is a processor state of the integrated circuit device where the integrated circuit device is a processor.

Assignees

• Wells Ryan D
• Ananthakrishnan Avinash N
• Rotem Efraim
• Rajwan Doron
• Andrew Gary A
• Intel Corp

Inventors

• Wells Ryan D
• Ananthakrishnan Avinash N
• Rotem Efraim
• Rajwan Doron
• Andrew Gary A

Classifications

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title