Integration of active devices with passive components and MEMS devices

US9751753B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9751753-B2
Application numberUS-201615256340-A
CountryUS
Kind codeB2
Filing dateSep 2, 2016
Priority dateApr 2, 2015
Publication dateSep 5, 2017
Grant dateSep 5, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Integration of active devices with passive components and MEMS devices is disclosed. An integrated semiconductor structure includes an active device having a device top electrode connected to a conductive jumper by a device-side via/interconnect metal stack. The integrated semiconductor structure also includes a passive component having a component bottom plate connected to the conductive jumper by a component side via/interconnect metal stack. The component bottom plate is situated at an intermediate metal level higher than the device top electrode, and the conductive jumper is situated at a connecting metal level higher than the component bottom plate. The conductive jumper reduces undesirable charge flow into the active device during fabrication of the passive component. The passive component can be, for example, a MEMS device.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of manufacturing an integrated semiconductor structure, the method comprising: forming an active device in a semiconductor substrate, the active device having a device top electrode; forming a first portion of a device-side via/interconnect metal stack, wherein the first portion of the device side via/interconnect metal stack is coupled to the device top electrode; forming a first portion of a passive component; forming a component-side via/interconnect metal stack, wherein the component-side via/interconnect metal stack is coupled to the first portion of said passive component; forming a second portion of said device-side via/interconnect metal stack, wherein the second portion of the device side via/interconnect metal stack is coupled to the first portion of the device side via/interconnect metal stack; and then forming a conductive jumper to connect said component-side via/interconnect metal stack to said second portion of said device-side via/interconnect metal stack. 2. The method of claim 1 , wherein the first portion of said passive component is situated at an intermediate metal level higher than the device top electrode of said active device. 3. The method of claim 1 , wherein said conductive jumper is situated at a connecting metal level higher than the first portion of said passive component. 4. The method of claim 3 , further comprising forming a second portion of the passive component over the first portion of the passive component, wherein the second portion of the passive component is situated at a metal layer below said connecting metal level. 5. The method of claim 3 , further comprising forming a second portion of the passive component over the first portion of the passive component, wherein the second portion of the passive component is situated at a same level as said connecting metal level. 6. The method of claim 1 , wherein said active device is configured to provide a driving signal to the first portion of said passive component through said conductive jumper. 7. The method of claim 1 , wherein said passive component is a microelectromechanical systems (MEMS) device. 8. The method of claim 7 , wherein said MEMS device comprises an actuation plate. 9. The method of claim 7 , wherein said MEMS device is a variable capacitor. 10. The method of claim 1 , wherein said active device comprises at least one CMOS transistor. 11. The method of claim 1 , wherein the forming a first portion of the device-side via/interconnect metal stack is formed through a first set of dielectric layers, the method further comprising forming an isolation structure within the first set of dielectric layers. 12. The method of claim 11 , wherein forming the isolation structure comprises forming a ground shield plate and shield sidewalls that extend from the ground shield plate. 13. The method of claim 11 , wherein the isolation structure is located between the semiconductor substrate and the first portion of the passive component. 14. The method of claim 1 , further comprising simultaneously forming at least portions of the passive component, the component-side via/interconnect metal stack and the second portion of the device-side via/interconnect metal stack. 15. The method of claim 1 , further comprising thermally and electrically isolating the first portion of the passive component from the active device during fabrication of the first portion of the passive component. 16. The method of claim 1 , further comprising forming a second portion of the passive component over the first portion of the passive component. 17. The method of claim 16 , further comprising forming the second portion of the passive component and the conductive jumper from a common metal layer. 18. The method of claim 3 , further comprising forming a second portion of the passive component over the first portion of the passive component, wherein the second portion of the passive component is situated above said connecting metal level. 19. The method of claim 1 , wherein the conductive jumper forms an electrical path between the passive component and the active device.

Assignees

Inventors

Classifications

  • Stacking the electronic processing unit and the micromechanical structure · CPC title

  • the micromechanical device and the control or processing electronics being integrated on the same substrate · CPC title

  • Methods for preserving structures not provided for in groups B81C1/00785 - B81C1/00825 · CPC title

  • Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate · CPC title

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Frequently asked questions

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What does patent US9751753B2 cover?
Integration of active devices with passive components and MEMS devices is disclosed. An integrated semiconductor structure includes an active device having a device top electrode connected to a conductive jumper by a device-side via/interconnect metal stack. The integrated semiconductor structure also includes a passive component having a component bottom plate connected to the conductive jumpe…
Who is the assignee on this patent?
Newport Fab Llc
What technology area does this patent fall under?
Primary CPC classification B81C1/00246. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Sep 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).