Test Pattern for Compensating for a Lateral Offset in the Detection of an Impaired Nozzle
US-2024408893-A1 · Dec 12, 2024 · US
US9751320B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9751320-B2 |
| Application number | US-201315024339-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 27, 2013 |
| Priority date | Sep 27, 2013 |
| Publication date | Sep 5, 2017 |
| Grant date | Sep 5, 2017 |
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A printhead with a separate address generator for ink level sensors is described. In an example, a printhead includes drop ejectors fluidically coupled to nozzles, at least one nozzle address generator, nozzle decoders coupled to nozzle address generator(s) and the drop ejectors, ink level sensors each having a sensor circuit in a sensor chamber and a purging resistor circuit, a sensor address generator, and sensor decoders coupled to the sensor address generator and the purging resistor circuit in each of the ink level sensors.
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What is claimed is: 1. A printhead, comprising: drop ejectors fluidically coupled to nozzles; at least one nozzle address generator; nozzle decoders coupled to the at least one nozzle address generator and the drop ejectors; ink level sensors each having a sensor circuit in a sensor chamber and a purging resistor circuit a sensor address generator; and sensor decoders coupled to the sensor address generator and the purging resistor circuit in each of the ink level sensors. 2. The printhead of claim 1 , wherein the at least one nozzle address generator and the sensor address generator are coupled to a control line and a plurality of clock lines. 3. The printhead of claim 2 , wherein the at least one nozzle address generator is responsive to first pulse patterns on the control line, and wherein the sensor address generator is responsive to second pulse patterns on the control line. 4. The printhead of claim 3 , wherein the second pulse patterns includes a pulse pattern causing the sensor address generator to address a first portion of the sensor decoders, and a second pulse pattern causing the sensor address generator to address a second portion of the sensor decoders. 5. The printhead of claim 1 , wherein the at least one nozzle address generator generates addresses in an address space equal to a number of the drop ejectors. 6. A method of controlling a printhead, comprising: receiving pulse patterns on a control line related to clock signals on clock lines; generating addresses using at least one address generator for addressing drop ejectors responsive to first pulse patterns on the control line; and generating addresses using an additional address generator for addressing purging resistor circuits for ink level sensors responsive to second pulse patterns on the control line. 7. The method of claim 6 , wherein the at least one address generator generates addresses in an address space equal to a number of the drop ejectors. 8. The method of claim 7 , wherein the number of drop ejectors and a number of purging resistor circuits exceed the number of addresses in the address space. 9. An apparatus, comprising: a firing resistor array having resistors to thermally eject ink from nozzles; a sensor purging resistor array having purging resistor circuits for purging ink residue from ink level sensors; nozzle decoders to selectively couple energy on fire lines to the resistors; sensor decoders to selectively couple energy on the fire lines to the purging resistor circuits; at least one address generator to provide address signals to the nozzle decoders; and an additional address generator to provide address signals to the sensor decoders. 10. The apparatus of claim 9 , further comprising: clock lines to provide clock signals to the at least one address generator and the additional address generator; and a control line to provide pulse patterns related to the clock signals on clock lines, the pulse patterns having first pulse patterns detectable by the at least one address generator and second pulse patterns detectable by the additional address generator.
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