Method and apparatus for aggregating and encoding received symbols including generation of a pointer for a control code

Patent metadata

Field	Value
Publication number	US-9749237-B2
Application number	US-201514625832-A
Country	US
Kind code	B2
Filing date	Feb 19, 2015
Priority date	Feb 21, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A data processing system including an interface and an encoder. The interface is configured to receive first symbols from one or more ports. The interface is configured to aggregate a predetermined number of the first symbols to provide second symbols. The encoder is configured to (i) generate a header, and (ii) encode the second symbols to generate third symbols, where the header indicates whether the third symbols include a set of control codes. Responsive to the third symbols including the set of control codes, the encoder is configured to generate a pointer for the set of control codes, where the pointer can assume more values than are in the set of control codes.

First claim

What is claimed is:

1. A data processing system comprising:
an interface configured to receive a first plurality of symbols from one or more ports, wherein the interface is configured to aggregate a predetermined number of the first plurality of symbols to provide a second plurality of symbols; and
an encoder configured to (i) generate a header, and (ii) encode the second plurality of symbols to generate a third plurality of symbols, wherein the header indicates whether the third plurality of symbols includes a set of control codes,
wherein, responsive to the third plurality of symbols including the set of control codes, the encoder is configured to generate a pointer for the set of control codes, and wherein the pointer includes at least two more bits than are in the set of control codes.

2. The data processing system of claim 1 , wherein:
the one or more ports includes a plurality of ports;
the interface is configured to receive the first plurality of symbols in an arbitrary order; and
the first plurality of symbols includes control symbols and data symbols in an arbitrary order.

3. The data processing system of claim 2 , wherein:
some of the first plurality of symbols includes start control bits;
the start control bits correspond respectively to the plurality of ports; and
each of the start control bits indicates a start of a respective packet.

4. The data processing system of claim 1 , wherein the encoder is configured to selectively include control codes in any of the third plurality of symbols.

5. The data processing system of claim 1 , wherein the header has only a single bit.

6. The data processing system of claim 1 , wherein the one or more ports includes only a single port.

7. The data processing system of claim 1 , wherein:
each of the symbols in the third plurality of symbols includes a first plurality of bits;
the pointer includes a second plurality of bits;
the set of control codes includes a third plurality of bits; and
a number of bits in the first plurality of bits is greater than or equal to a number of bits in the second plurality of bits plus a number of bits in the third plurality of bits.

8. The data processing system of claim 1 , wherein:
the encoder is configured to generate an encoded block;
the encoded block includes the third plurality of symbols; and
a number of symbols in the encoded block is less than or equal to 2 P , where P is a number of bits in the pointer.

9. The data processing system of claim 1 , wherein the second plurality of symbols includes only ten symbols.

10. The data processing system of claim 1 , wherein:
each symbol in the first plurality of symbols includes only ten bits; and
the ten bits include eight data bits and two control bits.

11. The data processing system of claim 1 , wherein:
the first plurality of symbols comprise a plurality of data symbols and a plurality of control codes; and
the set of control codes is based on the plurality of control codes.

12. The data processing system of claim 1 , further comprising: a scrambler configured to scramble the third plurality of symbols;
a gearbox configured to format an output of the scrambler; and a serializer/deserializer (SERDES) device configured to serialize an output of the gearbox.

13. The data processing system of claim 1 , wherein:
one of the third plurality of symbols includes the set of control codes; and
each control code in the set of control codes is a bit of the set of control codes.

14. The data processing system of claim 13 , wherein the one of the third plurality of symbols includes the pointer.

15. The data processing system of claim 1 , wherein the pointer comprises a bit indicating whether a next set of control codes of a next symbol in the third plurality of symbols is a last set of control codes in the third plurality of symbols.

16. The data processing system of claim 15 , wherein:
the encoder is configured to generate an encoded block;
the encoded block includes the third plurality of symbols; and
a number of symbols in the encoded block is equal to 2 P−1 , where P is a number of bits in the pointer.

17. The data processing system of claim 1 , wherein the pointer points to a location where the set of control codes is located in the third plurality of symbols.

18. A method comprising:
receiving at an interface a first plurality of symbols from one or more ports;
aggregating a predetermined number of the first plurality of symbols to provide a second plurality of symbols;
generating a header; and
encoding, by an encoder, the second plurality of symbols to generate a third plurality of symbols,
wherein
the header indicates whether the third plurality of symbols includes a set of control codes,
the encoder is configured to, responsive to the third plurality of symbols including the set of control codes, generate a pointer for the set of control codes, and the pointer includes at least two more bits than are in the set of control codes.

19. The method of claim 18 , wherein:
the one or more ports includes a plurality of ports;
the first plurality of symbols are received at the interface in an arbitrary order;
some of the first plurality of symbols includes start control bits;
the start control bits correspond respectively to the plurality of ports; and
each of the start control bits indicates a start of a respective packet.

20. The method of claim 18 , further comprising selectively including control codes in any of the third plurality of symbols,
wherein the header has only a single bit.

21. The method of claim 18 , wherein the one or more ports includes only a single port.

22. The method of claim 18 , wherein:
each of the symbols in the third plurality of symbols includes a first plurality of bits;
the pointer includes a second plurality of bits;
the set of control codes includes a third plurality of bits; and
a number of bits in the first plurality of bits is greater than or equal to a number of bits in the second plurality of bits plus a number of bits in the third plurality of bits.

23. The method of claim 18 , comprising generating an encoded block, wherein:
the encoded block includes the third plurality of symbols; and
a number of symbols in the encoded block is less than or equal to 2 P , where P is a number of bits in the pointer.

24. The method of claim 18 , wherein
the second plurality of symbols includes only ten symbols;
each symbol in the first plurality of symbols includes only ten bits; and
the ten bits include eight data bits and two control bits.

25. The method of claim 18 , wherein:
one of the third plurality of symbols includes the set of control codes; and
each control code in the set of control codes is a bit of the set of control codes.

Assignees

• Marvell World Trade Ltd

Inventors

• Lo William

Classifications

• H04L25/4908 Primary

  using mBnB codes · CPC title

• H04L45/74 Primary

  Address processing for routing · CPC title