Receiver bandwidth adaptation

Patent metadata

Field	Value
Publication number	US-9749162-B1
Application number	US-201615084026-A
Country	US
Kind code	B1
Filing date	Mar 29, 2016
Priority date	Mar 29, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

An apparatus for processing data includes a linear equalizer, a load switchably connected to an output of the linear equalizer, a slicer configured to sample a signal derived from the output of the linear equalizer, and a detector circuit configured to detect an over-equalization condition in data to be sampled by the slicer and to connect the load to the output of the linear equalizer in the over-equalization condition.

First claim

What is claimed is:

1. An apparatus for processing data, comprising:
a linear equalizer;
a load switchably connected to an output of the linear equalizer;
a slicer that samples a signal derived from the output of the linear equalizer; and
a detector circuit that detects an over-equalization condition in data to be sampled by the slicer and to connect the load to the output of the linear equalizer in the over-equalization condition.

2. The apparatus of claim 1 , wherein the detector circuit is connects the load to the output of the linear equalizer in the over-equalization condition only when a boost setting in the linear equalizer is at a minimum level.

3. The apparatus of claim 1 , wherein the linear equalizer comprises a continuous time linear equalizer.

4. The apparatus of claim 1 , wherein the detector circuit detects the over-equalization condition in an input to the linear equalizer.

5. The apparatus of claim 1 , wherein the detector circuit detects the over-equalization condition in the output of the linear equalizer.

6. The apparatus of claim 1 , wherein the over-equalization condition comprises an inner eye height of the data to be deserialized being greater than an outer eye height of the input to the linear equalizer.

7. The apparatus of claim 1 , wherein the detector circuit comprises a data latch and an error latch that sample the data at an inner eye level and an outer eye level.

8. The apparatus of claim 1 , wherein the detector circuit comprises a comparator that compares absolute values of eye levels.

9. The apparatus of claim 8 , wherein the comparator indicates the over-equalization condition when the absolute value of the eye level magnitude for a data pattern ‘110’ is less than the absolute value of the eye level magnitude for a data pattern ‘101’.

10. The apparatus of claim 8 , wherein the comparator indicates the over-equalization condition when the absolute value of the eye level magnitude or a data pattern ‘001’ is less than the absolute value of the eye level magnitude for a data pattern ‘010’.

11. The apparatus of claim 1 , further comprising a decision circuit that samples an analog signal from the output of the linear equalizer to yield digital data samples as the data to be deserialized.

12. A method for deserializing data, comprising:
equalizing an analog signal in a continuous time linear equalizer in a deserializer receiver;
determining whether the analog signal is over-equalized;
reducing a bandwidth of the deserializer receiver when the analog signal is over-equalized by connecting a load to an output of the continuous time linear equalizer;
converting the analog signal to digital data; and
deserializing the digital data.

13. The method of claim 12 , wherein the bandwidth of the deserializer receiver is only reduced when the analog signal is over-equalized and when a boost applied by the continuous time linear equalizer is at a minimum value.

14. The method of claim 12 , wherein determining whether the analog signal is over-equalized comprises setting a latch level at an inner eye level and at an outer eye level and sampling the analog signal at the latch levels.

15. The method of claim 14 , wherein determining whether the analog signal is over-equalized further comprises comparing an absolute value of the sampled analog signal at the inner eye level with an absolute value of the sampled analog signal at the outer eye level, wherein the analog signal is over-equalized when the absolute value of the sampled analog signal at the inner eye level is greater than the absolute value of the sampled analog signal at the outer eye level.

16. The method of claim 14 , wherein the analog signal is sampled with the latch level at the inner eye level for a data pattern of ‘110’ and the analog signal is sampled with the latch level at the outer eye level for a data pattern of ‘101’.

17. The method of claim 14 , wherein the analog signal is sampled with the latch level at the inner eye level for a data pattern of ‘001’ and the analog signal is sampled with the latch level at the outer eye level for a data pattern of ‘010’.

18. A deserializer receiver comprising:
linear equalizer means for filtering the amplified signal to yield an equalized signal;
means for detecting an inner eye level and an outer eye level in the equalized signal;
means for detecting when the equalized signal is over-equalized; and
means for reducing a bandwidth of the deserializer receiver when the equalized signal is over-equalized by, wherein the detecting when the equalized signal is over-equalized comprises setting a latch level at the inner eye level and at the outer eye level and sampling the equalized signal at the latch levels.

19. The deserializer receiver of claim 18 , wherein the means for reducing a bandwidth of the deserializer receiver when the equalized signal is over-equalized is configured to reduce the bandwidth only when a boost applied by the linear equalizer is adapted to a minimum value.

20. The deserializer receiver of claim 18 , wherein the over-equalization detector comprises a comparator configured to compare absolute values of the inner eye level and the outer eye level.

Assignees

• Avago Technologies General Ip

Inventors

• Mobin Mohammad
• Xia Haitao

Classifications

• H04L2025/03707

  Detection or avoidance of local extrema · CPC title

• H04L25/03885 Primary

  adaptive · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title