Data transmitter, data receiver and smart device using the same

Patent metadata

Field	Value
Publication number	US-9749126-B2
Application number	US-201514980957-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 26, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Provided is a data transmitter including a signal interval determination unit configured to receive a data input signal corresponding to data to be transmitted, determine time intervals between a synchronization signal and a plurality of data signals according to the data input signal, and output interval signals corresponding to the intervals; a trigger generation unit configured to trigger according to an output signal from the signal interval determination unit; and a signal generation unit configured to receive the trigger to generate the synchronization signal and the data signals.

First claim

What is claimed is:

1. A data transmitter comprising:
a memory configured to store computer-readable instructions; and
one or more processors configured to execute the computer-readable instructions to cause the data transmitter to:
receive a data input signal corresponding to data to be transmitted;
determine time intervals, according to the data input signal, between a synchronization signal to be generated and a plurality of data signals to be generated;
output interval signals corresponding to the time intervals;
trigger according to the output interval signals; and
receive the trigger to generate the synchronization signal and the plurality of data signals.

2. The data transmitter of claim 1 , wherein the one or more processors execute the computer-readable instructions to further cause the data transmitter to:
receive a reference signal and a first data input signal to output, from the reference signal, a first interval signal having an interval that corresponds to the first data input signal; and
receive the first interval signal and a second data input signal to output, from the first interval signal, a second interval signal having an interval that corresponds to the second data input signal.

3. The data transmitter of claim 2 , wherein the one or more processors execute the computer-readable instructions to further cause the data transmitter to receive an N−1th interval signal and an Nth data input signal to output, from the N−1th interval signal, an Nth interval signal having an interval that corresponds to the Nth data input signal, where N is a natural number larger than or equal to 3.

4. The data transmitter of claim 2 , wherein the one or more processors execute the computer-readable instructions to further cause the data transmitter to:
delay and output a first input signal by a predetermined delay time by a cascade connection of delay cells; and
select one of signals outputted from the delay cells according to a second input signal,
wherein the first input signal and the second input signal are the reference signal and the first data input signal, respectively, and the first input signal and the second input signal are the first interval signal and the second data input signal, respectively.

5. The data transmitter of claim 3 , wherein the one or more processors execute the computer-readable instructions to further cause the data transmitter to:
delay and output a first input signal by a predetermined delay time by a cascade connection of delay cells; and
select one of signals outputted from the delay cells, wherein the first input signal and a second input signal is the N−1th interval signal and the Nth data input signal, respectively.

6. The data transmitter of claim 2 , wherein the one or more processors execute the computer-readable instructions to further cause the data transmitter to receive the reference signal, the first interval signal, and the second interval signal to perform an OR operation.

7. The data transmitter of claim 6 , wherein the one or more processors execute the computer-readable instructions to further cause the data transmitter to:
receive the reference signal and an inverted reference signal that is obtained by inverting the reference signal, perform an AND operation, and output a value to the OR operation;
receive the first interval signal and a first inverted interval signal that is obtained by inverting the first interval signal, perform an AND operation, and output a value to the OR operation; and
receive the second interval signal and a second inverted interval signal that is obtained by inverting the second interval signal, perform an AND operation, and output a value to the OR operation.

8. The data transmitter of claim 6 , wherein the one or more processors execute the computer-readable instructions to further cause the data transmitter to:
receive a trigger corresponding to the reference signal to generate the synchronization signal;
receive a trigger corresponding to the first interval signal to generate a first data signal; and
receive a trigger corresponding to the second interval signal to generate a second data signal.

Assignees

• Industry-Academic Cooperation Foundation Yonsei Univ

Inventors

• Kim Tae Wook
• Jung Taek Hyun
• Lee Geun-Haeng

Classifications

• H03K5/15066

  using bistable devices (H03K5/15093 takes precedence) · CPC title

• H03K5/15046

  using a tapped delay line · CPC title

• H04L7/04 Primary

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H03K5/1502

  programmable · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title